DAC7631 datasheet(16/24 Pages) TI2

16 / 24 page

DAC7631

DAC updates; i.e., the LDAC pin can be driven with a

separate signal, such as a timing clock, which need not be

directly related to the serial data timing. This makes it easy

to synchronize DAC7631 updates with external events or

with other DACs.

Note that CS and CLK are combined with an OR gate, which

controls the serial-to-parallel shift register. These two inputs

are completely interchangeable. In addition, care must be

taken with the state of CLK when CS rises at the end of a

serial transfer. If CLK is LOW when CS rises, the OR gate

will provide a rising edge to the shift register, shifting the

internal data one additional bit. The result will be incorrect

data and possible selection of the wrong input register(s). If

both CS and CLK are used, CS should rise only when CLK

is HIGH. If not, then either CS or CLK can be used to

operate the shift register. See Table II for more information.

DIGITAL TIMING

Figure 15 and Table III provide detailed timing for the

digital interface of the DAC7631.

DIGITAL INPUT CODING

The DAC7631 input data is in Straight Binary format. The

output voltage is given by Equation 1:

OUT

REF

=+ ()

–•

65 536

(1)

where N is the digital input code. This equation does not

include the effects of offset (zero-scale) or gain (full-scale)

errors.

DIGITALLY-PROGRAMMABLE

CURRENT SOURCE

The DAC7631 offers a unique set of features that allows a

wide range of flexibility in designing applications circuits

such as programmable current sources. The DAC7631 offers

both a differential reference input, as well as an open-loop

configuration around the output amplifier. The open-loop

configuration around the output amplifier allows a transistor

to be placed within the loop to implement a digitally-

programmable, unidirectional current source. The availabil-

ity of a differential reference allows programmability for

both the full-scale and zero-scale currents. The output cur-

rent is calculated as:

VL R

OUT

REF

SENSE

REF

SENSE

























()

–

•

65 536

(2)

CS(1)

CLK(1)

LOAD

RST

SERIAL SHIFT REGISTER

H(2)

X(3)

No Change

L(4)

No Change

↑(5)

Advanced One Bit

↑

Advanced One Bit

H(6)

XL(7)

No Change

H(6)

↑(8)

No Change

NOTES: (1) CS and CLK are interchangeable. (2) H = Logic HIGH.

(3) X = Don’t Care. (4) L = Logic LOW (5) = Positive Logic Transition.

(6) A HIGH value is suggested in order to avoid a “false clock” from

advancing the shift register and changing the shift register. (7) If data is

clocked into the serial register while LOAD is LOW, the DAC register will

change. This will corrupt the data in each DAC register that has been

erroneously selected. (8) Rising edge of RST causes no change in the

contents of the serial shift register.

TABLE II. Serial Shift Register Truth Table.

DAC7631

CLK

SDI

SCK

DIN

SDO

DAC7631

CLK

SDI

SDO

DAC7631

CLK

SDI

SDO

Other

Serial

Devices

FIGURE 14. Daisy-chaining DAC7631.

SERIAL-DATA OUTPUT

The Serial-Data Output (SDO) is the internal shift register’s

output. For DAC7631, the SDO is a driven output and does

not require an external pull-up. Any number of DAC7631’s

can be daisy chained by connecting the SDO pin of one

device to the SDI pin of the following device in the chain,

as shown in Figure 14.

DAC7631 Datasheet(PDF) 16 Page - Texas Instruments

DAC7631 Datasheet(HTML) 16 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Datasheet Download

Link URL