IN

SYNC

Power

On

Reset

VCC

LG

GND

Logic

BOOT

HG

SW

+5V

+

-

VIN

VOUT

Q1

Q2

Shoot-through

Protection

1

2

3

4

5

6

7

8

SW

HG

BOOT

IN

VCC

SYNC

GND

LG

GND

8

LG

7

VCC

6

SYNC

5

IN

4

BOOT

3

HG

2

SW

1

LM2724A

SNVS242C – JUNE 2003 – REVISED MARCH 2013

www.ti.com

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

CONNECTION DIAGRAM

Figure 1. 8-Lead SOIC

Figure 2. 8-Lead WSON

See Package Number D

See Package Number NGN

PIN DESCRIPTIONS

Pin

Name

Function

1

SW

Top driver return. Should be connected to the common node of top and bottom FETs

2

HG

Top gate drive output. Should be connected to the top FET gate.

3

BOOT

Bootstrap. Accepts a bootstrap voltage for powering the high-side driver

4

IN

Accepts a logic control signal

5

SYNC

Bottom gate enable

6

VCC

Connect to +5V supply

7

LG

Bottom gate drive output. Should be connected to the bottom FET gate.

8

GND

Ground

BLOCK DIAGRAM

2

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Product Folder Links: LM2724A