40k

100k

R1

R2

R3

C1

PWM

VOUT

COMP

CV

No Lead

Network

Required

ERROR

AMP

FB

TRK/SS

0.75V

CS

VOUT

Current

Sense Amp

1.27V

Negative Current

Comparator

1V

Low Side

Enable

VCL

Vbias

2.35V

ILIMIT SLOW

Gm = 5 mA/V

2V

ILIMIT FAST

CO

AV=16

FB

TRK/SS

CV

PWM

Comparator

CRMIX

to PWM

Latch

ERROR

AMP

0.75V

COMP

LM25115A

SNVS501B – FEBRUARY 2007 – REVISED APRIL 2013

www.ti.com

Valley current mode control improves the control loop stability and bandwidth. It also eliminates the R-C lead

network in the feedback path that is normally required with voltage mode control (Figure 22). Eliminating the lead

network not only simplifies the compensation, but also reduces sensitivity to output noise that could pass through

the lead network to the error amplifier.

The design of the voltage feedback path through the error amp begins with the selection of R1 and R2 in

Figure 22 to set the regulated output voltage. The steady state output voltage after soft-start is determined by the

following equation:

VOUT(final) = 0.75V x (1+R1/R2)

The parallel impedance of the R1, R2 resistor divider should be approximately 2k

Ω (between 0.5kΩ and 5kΩ).

Lower resistance values may not be properly driven by the error amplifier output and higher feedback resistances

can introduce noise sensitivity. The next step in the design process is selection of R3, which sets the ac gain of

the error amplifier.

The capacitor C1 is connected in series with R3 to increase the dc gain of the voltage regulation loop and

improve output voltage accuracy. The corner frequency set by R3 x C1 should be less than 1/10th of the cross-

over frequency of the overall converter such that capacitor C1 does not add phase lag at the crossover

frequency.

Figure 21. Current Sensing and Limiting

Figure 22. Voltage Sensing and Feedback

16

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