LM3532TME-40ASLASHNOPB datasheet(23/52 Pages) TI2

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Bit 7

Bit 6

Bit 5

Bit 4

R/W

Bit 0

Bit 1

I2C Compatible Address

MSB

LSB

Bit 3

Bit 2

SCL

SDIO

Data In

SDIO

Data Out

LM3532

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SNVS653E – JULY 2011 – REVISED AUGUST 2015

7.5 Programming

7.5.1 I2C-Compatible Interface

7.5.1.1 Start and Stop Conditions

The LM3532 is controlled via an I2C-compatible interface. START and STOP conditions classify the beginning

and the end of the I2C session. A START condition is defined as SDA transitioning from HIGH-to-LOW while SCL

is HIGH. A STOP condition is defined as SDA transitioning from LOW-to-HIGH while SCL is HIGH. The I2C

master always generates the START and STOP conditions. The I2C bus is considered busy after a START

condition and free after a STOP condition. During data transmission, the I2C master can generate repeated

START conditions. A START and a repeated START conditions are equivalent function-wise. The data on SDA

must be stable during the HIGH period of the clock signal (SCL). In other words, the state of SDA can only be

changed when SCL is LOW.

Figure 21. Start And Stop Sequences

7.5.1.2 I2C-Compatible Address

The 7-bit chip address for the LM3532 is (0x38) . After the START condition, the I2C master sends the 7-bit chip

address followed by an eighth bit (LSB) read or write (R/W). R/W = 0 indicates a WRITE and R/W = 1 indicates a

READ. The second byte following the chip address selects the register address to which the data is written. The

third byte contains the data for the selected register.

Figure 22. I2C-Compatible Chip Address (0x38)

7.5.1.3 Transferring Data

Every byte on the SDA line must be eight bits long, with the most significant bit (MSB) transferred first. Each byte

of data must be followed by an acknowledge bit (ACK). The acknowledge related clock pulse (9th clock pulse) is

generated by the master. The master then releases SDA (HIGH) during the 9th clock pulse. The LM3532 pulls

down SDA during the 9th clock pulse, signifying an acknowledge. An acknowledge is generated after each byte

has been received.

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