0

Bit 7

MSB

1

Bit 6

1

Bit 5

1

Bit 4

0

Bit 3

0

Bit 2

0

Bit 1

R/W

Bit 0

LSB

Serial Bus Slave Address (chip address)

LM3538

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SNVS674A – JUNE 2011 – REVISED MAY 2013

I

2C-COMPATIBLE INTERFACE

The LM3538 is controlled via an I2C compatible interface. START and STOP (Figure 22) conditions classify the

beginning and the end of the I2C session. A START condition is defined as SDA transitioning from HIGH to LOW

while SCL is HIGH. A STOP condition is defined as SDA transitioning from LOW to HIGH while SCL is HIGH.

The I2C master always generates START and STOP conditions. The I2C bus is considered busy after a START

condition and free after a STOP condition. During data transmission, the I2C master can generate repeated

START conditions. A START and a repeated START conditions are equivalent function-wise. The data on SDA

must be stable during the HIGH period of the clock signal (SCL). In other words, the state of SDA can only be

changed when SCL is LOW.

Figure 22. Start and Stop Sequences

I2C-COMPATIBLE CHIP ADDRESS

The chip address for the LM3538 is 0111000 (38h). After the START condition, the I2C master sends the 7-bit

chip address followed by a read or write bit (R/W). R/W= 0 indicates a WRITE and R/W = 1 indicates a READ.

The second byte following the chip address selects the register address to which the data will be written. The

third byte contains the data for the selected register.

Figure 23. Chip Address

TRANSFERRING DATA

Every byte on the SDA line must be eight bits long, with the most significant bit (MSB) transferred first. Each byte

of data must be followed by an acknowledge bit (ACK). The acknowledge related clock pulse (9th clock pulse) is

generated by the master. The master releases SDA (HIGH) during the 9th clock pulse. The LM3538 pulls down

SDA during the 9th clock pulse, signifying an acknowledge. An acknowledge is generated after each byte has

been received. Figure 24 is an example of a write sequence to the DIODE ENABLE register of the LM3538.

Figure 24. Write Sequence to the LM3538

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