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AFE5804 Datasheet(PDF) 12 Page - Texas Instruments |
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AFE5804 Datasheet(HTML) 12 Page - Texas Instruments |
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12 / 63 page ![]() D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 Sample n Sample n+12 t PROP t (A) D 12clockslatency ADC Input (1) Clock Input 6XFCLK LCLKM LCLKP 1XFCLK FCLKM FCLKP SERIAL DATA OUTP OUTM t SAMPLE Sample n+13 t H1 t SU1 t H2 t SU2 LCLKM LCLKP OUTM OUTP t =min(t ,t ) t =min(t ,t ) SU SU1 SU2 H H1 H2 AFE5804 SBOS442C – JUNE 2008 – REVISED OCTOBER 2011 www.ti.com (1) Referenced to ADC Input (internal node) for illustration purposes only. Figure 1. LVDS Timing Diagram Figure 2. Definition of Setup and Hold Times TIMING CHARACTERISTICS (1) AFE5804 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tD(A) ADC aperture delay 1.5 4.5 ns Aperture delay variation Channel-to-channel within the same device (3 σ) ±20 ps tJ Aperture jitter 400 fS, rms Time to valid data after coming out of 50 μs COMPLETE POWER-DOWN mode Time to valid data after coming out of PARTIAL tWAKE Wake-up time POWER-DOWN mode (with clock continuing to 2 μs run during power-down) Time to valid data after stopping and restarting 40 μs the input clock Clock Data latency 12 cycles (1) Timing parameters are ensured by design and characterization; not production tested. 12 Copyright © 2008–2011, Texas Instruments Incorporated |
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