SN74ACT2226, SN74ACT2228

DUAL 64

× 1, DUAL 256 × 1

CLOCKED FIRST-IN, FIRST-OUT MEMORIES

SCAS219C – JUNE 1992 – REVISED OCTOBER 1997

12

POST OFFICE BOX 655303

APPLICATION INFORMATION

An example of concentrating two independent serial-data signals into a single composite data signal with the use of

an SN74ACT2226 or SN74ACT2228 device is shown in Figure 6. The input data to the FIFOs share the same average

(mean) frequency and the mean frequency of the SYS_CLOCK is greater than or equal to the sum of the individual

mean input rates. A single-bit FIFO is needed for each additional input data signal that is time-division multiplexed

into the composite signal.

The FIFO memories provide a buffer to absorb clock jitter generated by the transmission systems of incoming signals

and synchronize the phase-independent inputs to one another. FIFO half-full (HF) flags are used to signal the

multiplexer to start fetching data from the buffers. The state of the flags also can be used to indicate when a FIFO

read should be suppressed to regulate the output flow (pulse-stuffing control). The FIFO almost-full/almost-empty

(AF/AE) flags can be used in place of the half-full flags to reduce transmission delay.

1HF

1WRTCLK

1WRTEN

1D

1RDCLK

1RDEN

1Q

2HF

2D

2WRTEN

2WRTCLK

2Q

2RDEN

2RDCLK

READY_1

SELECT_1

DATA_1

SELECT_2

DATA_2

READY_2

SN74ACT2226

or

SN74ACT2228

Serial

Data

Stream

Serial

Data

Stream

+5 V

Time-Division

Multiplexer

SYS_CLOCK

Composite

Data Stream

Figure 6. Time-Division Multiplexing Using the SN74ACT2226 or SN74ACT2228