SLG51003 datasheet(23/72 Pages) RENESAS

23 / 72 page

SLG51003 Datasheet

R16DS0379EU0100, Rev. 1.00

Sep 12, 2024

Page 23

Functional Description

4.1

Main Operating States

SEQUENCE_DOWN

READY

CONFIG_INIT

• Read OTP and initialise configuration

• I2C Interface ON (If OTP Selection Bit Set)

• All digital resources are enabled

Normal Transition

Legend

Fault Transition

Fault Transition to Analog

RESET

Power down the supplies in a crash sequence

under following error conditions:

• CS De-assertion

• Over-temperature Detection

• Crash Detection

• Software Reset Request

• UVLO Detection

Error Conditions

SEQUENCE_DOWN Complete

LOW_IQ_RESET

No Over-temp AND

CS Asserted

CS Asserted AND

(VDD >

VDD_POR_UPPER)

• All Digital Logic in Reset State

• CS Detection Circuit Enabled

CS De-asserted OR

UVLO Detected

Figure 4. System State Machine Diagram

4.1.1.

LOW_IQ_RESET

If the CS is de-asserted or UVLO is detected, the SLG51003 enters its lowest power state (LOW_IQ_RESET)

and the device is disabled. It cannot leave LOW_IQ_RESET state while the CS is de-asserted.

4.1.2.

RESET

RESET state can be entered from:

▪

SEQUENCE_DOWN: if there was an error due to over-temperature, crash detect event, UVLO detection, or

a software reset was requested via I2C (if enabled), any enabled supplies will be disabled.

▪

LOW_IQ_RESET: following assertion of the CS and the VDD > VDD_POR_UPPER.

By entering RESET state, all digital logics get reset. A timer of 1.25 ms is started and state transitions from this

state cannot occur until the timer expires.

After the timer expires, transitions from this state are carried out as follows:

▪

If the CS is de-asserted or UVLO is detected, the SLG51003 transitions to LOW_IQ_RESET state.

▪

If no over-temperature condition is detected and the CS remains asserted, the SLG51003 transitions to

CONFIG_INIT state.

SLG51003 Datasheet(PDF) 23 Page - Renesas Technology Corp

SLG51003 Datasheet(HTML) 23 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72

Datasheet Download

Link URL