LM3485

SNVS178H – JANUARY 2002 – REVISED DECEMBER 2015

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7.4 Device Functional Modes

7.4.1 Start Up

The current limit circuit is active during start-up. During start-up the PFET will stay on until either the current limit

or the feedback comparator is tripped

If the current limit comparator is tripped first then the fold back characteristic should be taken into account. Start-

up into full load may require a higher current limit set point or the load must be applied after start-up.

One problem with selecting a higher current limit is inrush current during start-up. Increasing the capacitance

(CADJ) in parallel with RADJ results in soft-start. CADJ and RADJ create an RC time constant forcing current limit to

activate at a lower current. The output voltage will ramp more slowly when using the soft-start functionality. There

are example start-up plots for CADJ equal to 1 nF and 10 nF in Typical Characteristics. Lower values for CADJ will

have little to no effect on soft-start.

7.4.2 External Sense Resistor

The VDS of a PFET will tend to vary significantly over temperature. This will result an equivalent variation in

current limit. To improve current limit accuracy an external sense resistor can be connected from VIN to the

source of the PFET, as shown in Figure 26.

Figure 26. Current Sensing by External Resistor

7.4.3 PGATE

When switching, the PGATE pin swings from VIN (off) to some voltage below VIN (on). How far the PGATE will

swing depends on several factors including the capacitance, on time, and input voltage.

As shown in the Typical Characteristics, PGATE voltage swing will increase with decreasing gate capacitance.

Although PGATE voltage will typically be around VIN-5 V, with every small gate capacitances, this value can

increase to a typical maximum of VIN-8.3 V.

Additionally, PGATE swing voltage will increase as on time increases. During long on times, such as when

operating at 100% duty cycle, the PGATE voltage will eventually fall to its maximum voltage of VIN-8.3 V (typical)

regardless of the PFET gate capacitance.

The PGATE voltage will not fall below 0.4 V (typical). Therefore, when the input voltage falls below approximately

9 V, the PGATE swing voltage range will be reduced. At an input voltage of 7 V, for instance, PGATE will swing

from 7 V to a minimum of 0.4 V.

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