3

2

1

LSOUT-

BYPASS

C1N

GND

INR

SET

A

B

C

D

INM-

4

LSOUT+

SDA

I

2

CVDD

CPVSS

INL

LSVDD

C1P

HPL

HPR

INM+

CPGND

E

VDD

SCL

TI Confidential - NDA Restrictions

LM49151

www.ti.com

SNAS482F – MARCH 2009 – REVISED MARCH 2013

Connection Diagram

Figure 2. 20 Bump DSBGA Package

Top View

(See Package Number YZR0020)

BUMP DESCRIPTIONS

Bump

Name

Description

A1

I2CVDD

I2C Power Supply

A2

GND

Ground

A3

LSOUT-

Inverting Loudspeaker Output

A4

LSOUT+

Non-Inverting Loudspeaker Output

B1

VDD

Analog Power Supply

B2

SDA

I2C Data Input

B3

SCL

I2C Clock Input

B4

LSVDD

Loudspeaker Power Supply

C1

INL

Left Channel Input

C2

INR

Right Channel Input

C3

BYPASS

Mid-Rail Supply Bypass

C4

CPVSS

Charge Pump Output

D1

INM-

Mono Channel Inverting Input

D2

SET

ALC Timing Control

D3

CPN

Charge Pump Flying Capacitor - Negative Terminal

D4

CPP

Charge Pump Flying Capacitor - Positive Terminal

E1

INM+

Mono Channel Non-Inverting Input

E2

HPR

Right Channel Headphone Amplifier Output

E3

HPL

Left Channel Headphone Amplifier Output

E4

CPGND

Charge Pump Ground

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

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