CLKx

CLK_REQ x

Q

D

CLK signal

Inverter only

added for CLK2

SCLK_IN

CLK 1

CLK 2

LMH2191

www.ti.com

SNAS485D – JULY 2010 – REVISED MAY 2013

Figure 21. Clock Outputs

CLOCK REQUEST LOGIC

A clock request input is provided for each clock output. This allows the peripheral device to control when it wants

to receive a clock. In case the application does not have clock request functionality, the CLKx_REQ can be hard

wired to a logic high level to enable the clock output continuously. The clock request inputs have logic levels

compatible with 1.8V logic, but can tolerate logic high levels up to VBAT.

Figure 22. Enabling the output

The clock request logic enables an independent control of the clock tree driver outputs, CLK1 and CLK2, as well

as an LDO disable when both request inputs are low.

The on and off switching of the clock output drivers is done synchronously with the clock input in order to prevent

glitches at the clock output. For this the clock request signal is connected to the D input of a latch. The Q output

of this latch enables the clock output driver (see Figure 22). For the CLK1 output the CLK input signal is

connected via an inverter to the clock input of the latch. In this way the latch enables and disables the CLK1

output buffer on the falling edge of the clock signal. For the CLK2 output an extra inverter is inserted prior to the

latch circuit, and the CLK2 output buffer is enabled and disabled on the rising edge of the clock input signal

(equal to the falling edge of the CLK2 output signal).

LOW DROPOUT REGULATOR

The linear and Low-Dropout regulator (LDO) is used to regulate the input voltage, VBAT, thus generating a well-

defined ultra low noise 1.8V supply voltage. This allows the LMH2191 to suppress VBAT supply voltage ripple and

noise for the TCXO and the internal Clock Path. Voltage ripple and noise would distort clock edges causing extra

phase noise on the distributed clock signal.

The LDO is powered up whenever a Clock Request is active; it supports overheating detection and will switch off

in case overheating occurs. The recommended sequence for powering up the LDO is to raise a clock request to

a high level with the supply already powered up. Thus the LDO stays in shutdown mode with sub µA current

consumption until an output clock is actually needed. The LDO will power up within the turn-on time of about 200

µs (as specified in the data sheet tables). Alternatively, the clock request input can be hard wired to VBAT which

powers up the LDO simultaneously with VBAT. A drawback is that the LDO and clock path (and if connected, the

TCXO) will always draw current when VBAT is powered up. Also, in this setup, care should be taken with supplies

with an excessive long startup time of more than about 25 ms. Under this condition the LDO could exhibit

excessive long turn-on delay (order of seconds.)

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