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AD5066

Preliminary Technical Data

Rev. PrB | Page 14 of 20

INPUT SHIFT REGISTER

The AD5066 input shift register is 32 bits wide (see Figure 8).

The first four bits are don’t cares. The next four bits are the

command bits, C3 to C0 (see Table 8), followed by the 4-bit

DAC address bits, A3 to A0 (see Table 9) and finally the bit

data-word. The data-word comprises of 16-bit input code

followed by 4 don’t care bits for the AD5066 (see Figure 8).

These data bits are transferred to the DAC register on the 32nd

falling edge of SCLK.

SYNC INTERRUPT

In a normal write sequence, the SYNC line is kept low for at

least 32 falling edges of SCLK, and the DAC is updated on the

32nd falling edge. However, if SYNC is brought high before the

32nd falling edge, this acts as an interrupt to the write sequence.

The shift register is reset, and the write sequence is seen as

invalid. Neither an update of the DAC register contents nor a

change in the operating mode occurs (see Error! Reference

source not found.

ADDRESS BITS

COMMAND BITS

D15 D14 D13 D12 D11 D10

XXX

DB31 (MSB)

DB0 (LSB)

DATA BITS

Figure 8. AD5066 Input Register Content

POWER-ON RESET

The AD5066 contains a power-on reset circuit that controls the

output voltage during power-up. By connecting the POR pin

low, the AD5066 output powers up to 0 V; by connecting the

POR pin high, the AD5066 output powers up to midscale. The

output remains powered up at this level until a valid write

sequence is made to the DAC. This is useful in applications

where it is important to know the state of the output of the DAC

while it is in the process of powering up. There is also a software

executable reset function that resets the DAC to the power-on

reset code. Command 0111 is reserved for this reset function

(see Table 7). Any events on LDAC or CLR during power-on

reset are ignored.

POWER-DOWN MODES

The AD5066 contains four separate modes of operation.

Command 0100 is reserved for the power-down function (see

Table 7). These modes are software-programmable by setting

two bits, Bit DB9 and Bit DB8, in the control register (refer to

Table 12). Table 11 shows how the state of the bits corresponds

to the mode of operation of the device. Any or all DACs (DAC

A - DAC D) can be powered down to the selected mode by

setting the corresponding four bits (DB3, DB2, DB1, DB0) to 1.

See Table 12 for the contents of the input shift register during

power-down/

power-up operation.

When both Bit DB9 and Bit DB8, in the control register are set to

0, the part works normally with its normal power consumption

of TBD at 5 V. However, for the three power-down modes, the

supply current falls to TBD at 5 V (TBD at 3 V). Not only does

the supply current fall, but the output stage is also internally

switched from the output of the Dac to a resistor network of

known values. This has the advantage that the output

impedance of the part is known while the part is in power-

down mode. There are three different options. The output is

connected internally to GND through either a 1 kΩ or a 100 kΩ

resistor, or it is left open-circuited (three-state). The output

stage is illustrated in Figure 9.

The bias generator, resistor string, and other associated linear

circuitry are shut down when the power-down mode is activated.

However, the contents of the DAC register are unaffected when

in power-down. The time to exit power-down is typically 2.5 μs

for VDD = 5 V and VDD = 3 V (see Error! Reference source not

found.

Any combination of DACs can be powered up by setting PD1

and PD0 to 0 (normal operation). The output powers up to the

value in the input register (LDAC Low) or to the value in the

DAC register before powering down (LDAC high).

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