6

LP3470A

SNVSBF5C – JULY 2019 – REVISED MAY 2020

www.ti.com

Product Folder Links: LP3470A

Submit Documentation Feedback

Copyright © 2019–2020, Texas Instruments Incorporated

(1)

VIT+ = VHYS + VIT-

(2)

This parameter is guranteed by design and characterization

(3)

VPOR is the minimum VDD voltage level for a controlled output state. VDD slew rate ≤ 100mV/µs

7.5 Electrical Characteristics

At 0.95 V

≤ VCC ≤ 10 V, SRT = Open, RESET pull-up resistor (Rpull-up) = 100 kΩ to VCC, output reset load (CLOAD) = 10 pF and

over the operating free-air temperature range – 40°C to 125°C, unless otherwise noted. Typical values are at TJ = 25°C.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VCC

Input supply voltage

0.95

10

V

VIT-

Negative-going input threshold accuracy

-40°C to 125°C

–1.5

1

1.5

%

VHYS

Hysteresis on VIT- pin

VIT- = 3.08 V to 4.63 V

175

200

225

mV

VHYS

Hysteresis on VIT- pin

VIT- = 2.64 V to 2.93 V

75

100

125

mV

ICC

Supply current into VCC pin

VCC = 0.95 V < VCC < 10 V

VCC > VIT+

(1)

TA = -40°C to 125°C

0.3

1

µA

RSRT

SRT pin internal resistance (2)

350

500

650

kΩ

VPOR

Power on Reset Voltage(3)

VOL(max) = 0.2 V

IOUT (Sink) = 5.6 uA

950

mV

VOL

Low level output voltage

1.5 V < VCC < 5 V

VCC < VIT-

IOUT(Sink) = 2 mA

200

mV

Ilkg(OD)

Open-Drain output leakage current

RESET pin in High Impedance,

VCC = VRESET = 5.5 V

VIT+ < VCC

90

nA

(1)

tP_HL measured from threhold trip point (VIT-) to VOL

(2)

Ideal capacitor

(3)

Parameter is guranteed by design.

(4)

Overdrive % = [(VCC/ VIT-) - 1] × 100%

7.6 Timing Requirements

At 0.95 V

≤ VCC ≤ 10 V, SRT = Open, RESET pull-up resistor (Rpull-up) = 100 kΩ to VCC, output reset load (CLOAD) = 10 pF and

over the operating free-air temperature range – 40°C to 125°C, VCC slew rate < 100mV / us, unless otherwise noted. Typical

values are at TJ = 25°C.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

tP_HL

Propagation detect delay for VCC falling

below VIT-

VCC = VIT+ to (VIT-) - 10%

(1)

15

30

µs

tD

Reset time delay

SRT pin = open

VCC = (VIT- -1V) to (VIT+ + 1V)

50

µs

SRT pin = 10 nF(2)(3)

6.2

ms

SRT pin = 1 µF(2)(3)

619

ms

tGI_VIT-

Glitch immunity VIT-

5% VIT- overdrive

(3) (4)

10

µs