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LAN9252V/ML Datasheet(PDF) 117 Page - Microchip Technology

Part # LAN9252V/ML
Description  2/3-Port EtherCAT® Slave Controller with Integrated Ethernet PHYs
PDF  329 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

LAN9252V/ML Datasheet(HTML) 117 Page - Microchip Technology

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 2015 Microchip Technology Inc.
DS00001909A-page 117
LAN9252
10.2.6.4
Dual Address / Data Write
The SPI Dual Address / Data Write instruction inputs the instruction code one bit per clock and the address and data
bytes two bits per clock. This instruction is supported in SPI bus protocol only with clock frequencies up to 80 MHz. This
instruction is not supported in SQI bus protocol.
The SPI slave interface is selected by first bringing SCS# active. The 8-bit SDADW instruction, B2h, is input into the
SIO[0] pin, followed by the two address bytes into the SIO[1:0] pins. The address bytes specify a BYTE address within
the device.
The data follows the address bytes. The data is input into the SIO[1:0] pins starting with the msbs of the LSB. The
remaining di-bits are shifted in on subsequent clock edges. The data write to the register occurs after the 32-bits are
input. In the event that 32-bits are not written when the SCS# is returned high, the write is considered invalid and the
register is not affected.
The SCS# input is brought inactive to conclude the cycle.
Figure 10-15 illustrates a typical single and multiple register dual address / data write.
FIGURE 10-15:
SPI DUAL ADDRESS / DATA WRITE
SPI Dual Address / Data Write Single Register
SCK (active high)
SIO0
011
X
Instruction
1
SIO1
Data
...
...
SPI Dual Address / Data Write Multiple Registers
00
Z
X
SCK (active low)
SCS#
...
X
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
X
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
2
9
3
0
3
1
3
2
X
X
2
9
3
0
3
1
3
2
1
7
1
8
1
9
1
7
1
8
1
9
SCK (active high)
SIO0 X
Instruction
SIO1
...
SCK (active low)
SCS#
...
X
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
X
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
X
X
1
7
1
8
1
9
1
7
1
8
1
9
...
...
...
Data 1...
Data m
Data m+1... Data n
...
0
Data
...
D
7
D
6
D
5
Z
X
D
2
9
D
2
5
D
4
D
3
D
2
D
2
4
D
2
8
D
2
6
D
2
7
X
...
...
Data 1...
Data m
Data m+1... Data n
D
7
D
5
D
3
D
2
9
D
2
5
D
2
7
D
7
D
5
D
3
Z
X
D
2
9
D
2
5
D
2
7
D
6
D
4
D
2
D
2
4
D
2
8
D
2
6
D
6
D
4
D
2
D
2
4
D
2
8
D
2
6
X
1
Address
d
e
c
A
1
3
i
n
c
A
1
2
A
1
1
A
1
0
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
Address
Z
Address
d
e
c
A
1
3
i
n
c
A
1
2
A
1
1
A
1
0
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
Address
011
1
00
0
1



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