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LAN9252V/ML Datasheet(PDF) 121 Page - Microchip Technology

Part # LAN9252V/ML
Description  2/3-Port EtherCAT® Slave Controller with Integrated Ethernet PHYs
PDF  329 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

LAN9252V/ML Datasheet(HTML) 121 Page - Microchip Technology

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 2015 Microchip Technology Inc.
DS00001909A-page 121
LAN9252
A block diagram of the main components of each PHY can be seen in Figure 11-1.
11.2.2
100BASE-TX TRANSMIT
The 100BASE-TX transmit data path is shown in Figure 11-2. Shaded blocks are those which are internal to the PHY.
Each major block is explained in the following sections.
11.2.2.1
100BASE-TX Transmit Data Across the Internal MII Interface
For a transmission, the EtherCAT Core MAC drives the transmit data onto the internal MII TXD bus and asserts the inter-
nal MII TXEN to indicate valid data. The data is in the form of 4-bit wide 25 MHz data.
FIGURE 11-1:
PHY BLOCK DIAGRAM
FIGURE 11-2:
100BASE-TX TRANSMIT DATA PATH
HP Auto-MDIX
TXPx/TXNx
RXPx/RXNx
To External
Port x Ethernet Pins
100
Transmitter
100
Reciever
MII
MAC
Interface
MII
MDIO
Auto-
Negotiation
To Port x
EtherCAT MAC
To EtherCAT
core
PLL
PHY Management
Control
Registers
From
System Clocks Controller
Interrupts
To System
Interrupt Controller
Port x
MAC
100M
TX Driver
MLT-3
Converter
NRZI
Converter
4B/5B
Encoder
Magnetics
CAT-5
RJ45
100M
PLL
Internal
MII 25 MHz by 4 bits
Internal
MII Transmit Clock
25MHz by
5 bits
NRZI
MLT-3
MLT-3
MLT-3
MLT-3
Scrambler
and PISO
125 Mbps Serial
MII MAC
Interface
25MHz
by 4 bits



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