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LAN9252V/ML Datasheet(PDF) 123 Page - Microchip Technology

Part # LAN9252V/ML
Description  2/3-Port EtherCAT® Slave Controller with Integrated Ethernet PHYs
PDF  329 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

LAN9252V/ML Datasheet(HTML) 123 Page - Microchip Technology

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 2015 Microchip Technology Inc.
DS00001909A-page 123
LAN9252
11.2.2.3
Scrambler and PISO
Repeated data patterns (especially the IDLE code-group) can have power spectral densities with large narrow-band
peaks. Scrambling the data helps eliminate these peaks and spread the signal power more uniformly over the entire
channel bandwidth. This uniform spectral density is required by FCC regulations to prevent excessive EMI from being
radiated by the physical wiring.
The seed for the scrambler is generated from the PHY address, ensuring that each PHY will have its own scrambler
sequence. For more information on PHY addressing, refer to Section 11.1.1, "PHY Addressing".
The scrambler also performs the Parallel In Serial Out conversion (PISO) of the data.
11.2.2.4
NRZI and MLT-3 Encoding
The scrambler block passes the 5-bit wide parallel data to the NRZI converter where it becomes a serial 125MHz NRZI
data stream. The NRZI is then encoded to MLT-3. MLT-3 is a tri-level code where a change in the logic level represents
a code bit “1” and the logic output remaining at the same level represents a code bit “0”.
11.2.2.5
100M Transmit Driver
The MLT-3 data is then passed to the analog transmitter, which drives the differential MLT-3 signal on output pins TXPx
and TXNx, to the twisted pair media across a 1:1 ratio isolation transformer. The transmitter drives into the 100
 imped-
ance of the CAT-5 cable. Cable termination and impedance matching require external components.
11.2.2.6
100M Phase Lock Loop (PLL)
The 100M PLL locks onto the reference clock and generates the 125 MHz clock used to drive the 125 MHz logic and
the 100BASE-TX Transmitter.
00110
/V/
INVALID, MII Receive Error (RXER) if
during MII Receive Data Valid (RXDV)
INVALID
11001
/V/
INVALID, MII Receive Error (RXER) if
during MII Receive Data Valid (RXDV)
INVALID
00000
/P/
INVALID
INVALID
00001
/V/
INVALID, MII Receive Error (RXER) if
during MII Receive Data Valid (RXDV)
INVALID
00010
/V/
INVALID, MII Receive Error (RXER) if
during MII Receive Data Valid (RXDV)
INVALID
00011
/V/
INVALID, MII Receive Error (RXER) if
during MII Receive Data Valid (RXDV)
INVALID
00101
/V/
INVALID, MII Receive Error (RXER) if
during MII Receive Data Valid (RXDV)
INVALID
01000
/V/
INVALID, MII Receive Error (RXER) if
during MII Receive Data Valid (RXDV)
INVALID
01100
/V/
INVALID, MII Receive Error (RXER) if
during MII Receive Data Valid (RXDV)
INVALID
10000
/V/
INVALID, MII Receive Error (RXER) if
during MII Receive Data Valid (RXDV)
INVALID
TABLE 11-1:
4B/5B CODE TABLE (CONTINUED)
Code Group
Sym
Receiver Interpretation
Transmitter Interpretation



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