LAN9252VSLASHML datasheet(124/329 Pages) MICROCHIP

124 / 329 page

LAN9252

DS00001909A-page 124

 2015 Microchip Technology Inc.

11.2.3

100BASE-TX RECEIVE

The 100BASE-TX receive data path is shown in Figure 11-3. Shaded blocks are those which are internal to the PHY.

Each major block is explained in the following sections.

11.2.3.1

100M Receive Input

The MLT-3 data from the cable is fed into the PHY on inputs RXPx and RXNx via a 1:1 ratio transformer. The ADC sam-

ples the incoming differential signal at a rate of 125M samples per second. Using a 64-level quantizer, 6 digital bits are

generated to represent each sample. The DSP adjusts the gain of the ADC according to the observed signal levels such

that the full dynamic range of the ADC can be used.

11.2.3.2

Equalizer, BLW Correction and Clock/Data Recovery

The 6 bits from the ADC are fed into the DSP block. The equalizer in the DSP section compensates for phase and ampli-

tude distortion caused by the physical channel consisting of magnetics, connectors, and CAT- 5 cable. The equalizer

can restore the signal for any good-quality CAT-5 cable between 1m and 100m.

If the DC content of the signal is such that the low-frequency components fall below the low frequency pole of the iso-

lation transformer, then the droop characteristics of the transformer will become significant and Baseline Wander (BLW)

on the received signal will result. To prevent corruption of the received data, the PHY corrects for BLW and can receive

the ANSI X3.263-1995 FDDI TP-PMD defined “killer packet” with no bit errors.

The 100M PLL generates multiple phases of the 125MHz clock. A multiplexer, controlled by the timing unit of the DSP,

selects the optimum phase for sampling the data. This is used as the received recovered clock. This clock is used to

extract the serial data from the received signal.

11.2.3.3

NRZI and MLT-3 Decoding

The DSP generates the MLT-3 recovered levels that are fed to the MLT-3 converter. The MLT-3 is then converted to an

NRZI data stream.

11.2.3.4

Descrambler

The descrambler performs an inverse function to the scrambler in the transmitter and also performs the Serial In Parallel

Out (SIPO) conversion of the data.

FIGURE 11-3:

100BASE-TX RECEIVE DATA PATH

Port x

MAC

A/D

Converter

MLT-3

Converter

NRZI

Converter

4B/5B

Decoder

Magnetics

CAT-5

RJ45

100M

PLL

Internal

MII 25MHz by 4 bits

Internal

MII Receive Clock

25MHz by

5 bits

NRZI

MLT-3

6 bit Data

Descrambler

and SIPO

125 Mbps Serial

DSP: Timing

recovery, Equalizer

and BLW Correction

MLT-3

MII MAC

Interface

25MHz

by 4 bits

LAN9252V/ML Datasheet(PDF) 124 Page - Microchip Technology

LAN9252V/ML Datasheet(HTML) 124 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL