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CLOCK-HALT RESET FUNCTIONS

Clock-Halt Reset

SCKI

T0081-01

48/fin or 48/fS

Fade-In Start

Fade-In Complete

Internal

Reset

Operation

Operation

DOUT

Normal Data

Normal Data

DOUT

(Contents)

Normal Data

SCKI Halt

SCKI Resume

Fixed to Low or High

t(CKR)

Reset: t(RST)

Reset Release: t(REL)

BPZ

Zero Data

PCM1807

SLES147 – SEPTEMBER 2005

The PCM1807 has a reset function, which is triggered by halting SCKI (pin 6) in both master and slave modes.

The function is available anytime after power on. Reset and power down are performed automatically 4

µs

(minimum) after SCKI is halted. While the clock-halt reset is asserted, the PCM1807 stays in the reset and

power-down mode, and DOUT is forced to zero. Also, all registers except the mode control registers are reset

once. If minimization of power dissipation is required, the PDWN bit must be set to HIGH prior to halting SCKI

through the serial control port as described in the SPI Serial Control Port for Mode Control section. SCKI must be

supplied to release the reset and power-down mode. The digital output is valid after the reset state is released

and the time of 1024 SCKI + 8960/fS has elapsed. Because the fade-in operation is performed, it takes additional

time of 48/fin or 48/fS until the level corresponding to the analog input signal is obtained. Figure 20 illustrates the

clock-halt reset timing.

To avoid ADC performance degradation, BCK (pin 8) and LRCK (pin 7) are required to synchronize with SCKI

within 4480/fS after SCKI is resumed. If it takes more than 4480/fS for BCK and LRCK to synchronize with SCKI,

SCKI should be masked until the synchronization is formed again, taking care of glitch and jitter. See the typical

circuit connection diagram, Figure 31

To avoid ADC performance degradation, the clock-halt reset also should be asserted when fS, SCKI, MD[1:0],

FMT bits, etc., are changed on the fly.

SYMBOL

PARAMETER

MIN

MAX

UNIT

t(CKR)

Delay time from SCKI halt to internal reset

4

µs

t(RST)

Delay time from SCKI resume to reset release

1024 SCKI

µs

t(REL)

Delay time from reset release to DOUT output

8960/fS

µs

Figure 20. Clock-Halt Reset Timing

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