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LOGIC DIAGRAM

(POSITIVE LOGIC)

1

2

3

4

6

7

A

B

R

RE

DE

D

ABSOLUTE MAXIMUM RATINGS

(1) (2)

SN65HVD10-EP,, SN65HVD11-EP

SN65HVD12-EP

SGLS278E – DECEMBER 2004 – REVISED SEPTEMBER 2007

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

ORDERING INFORMATION(1)

PACKAGE

SIGNALING RATE

UNIT LOADS

TA

SOIC MARKING

SOIC(2)(3)

25 Mbps

1/2

SN65HVD10QDREP

V10QEP

–40

°C to 125°C

10 Mbps

1/8

SN65HVD11QDREP(4)

V11QEP

1 Mbps

1/8

–40

°C to 85°C

SN65HVD12IDREP

V12IEP

25 Mbps

1/2

–55

°C to 125°C

SN65HVD10MDREP

V10MEP

(1)

For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

Web site at www.ti.com.

(2)

Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.

(3)

The D package is taped and reeled as indicated by the R suffix to the part number (i.e., SN65HVD10QDREP).

(4)

Product Preview

over operating free-air temperature range (unless otherwise noted)

SN65HVD10-EP

SN65HVD11-EP

SN65HVD12-EP

Supply voltage range, VCC

–0.3 V to 6 V

Voltage range at A or B

–9 V to 14 V

Input voltage range at D, DE, R, or RE

–0.5 V to VCC + 0.5 V

Voltage input range, transient pulse, A and B, through 100

Ω (see Figure 11)

–50 V to 50 V

A, B, and GND

16 kV

Human body model(3)

Electrostatic discharge

All pins

4 kV

Charged-device model(4)

All pins Charge

1 kV

See Package Dissipation

Continuous total power dissipation

Rating Table

Storage temperature range, Tstg

–65

°C to 150°C

Lead temperature 1,6 mm (1/16 in) from case for 10 s

260

°C

(1)

Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating

conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2)

All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.

(3)

Tested in accordance with JEDEC Standard 22, Test Method A114-A.

(4)

Tested in accordance with JEDEC Standard 22, Test Method C101.

2

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