ZSSC3230 Datasheet

R36DS0062ED0100 1.4

Jun 10, 2025

Page 21

© 2025 Renesas Electronics

▪ Bit 2 shows whether there has been a memory integrity/error as indicated by whether the checksum-based integrity

check passed or failed: 0 if the integrity test passed; 1 if the test failed.

▪ Bit 1 shows whether there has been an ADC overflow, which is detected if the raw ADC-output value for capacitive

measurement exceeded the nominal, digital ADC-output range, depending on the selected ADC resolution. This

check is only for the raw results for the capacitive measurement.

▪ Bit 0 shows the status Information regarding ALU saturation. If the last executed command was a measurement

request, this bit is 0 if any intermediate value and the final SSC result are in a valid range and no SSC-calculation

internal saturation occurred. If the last command was a measurement request, this bit is 1 if an SSC-calculation

internal saturation occurred. This bit is also 0 for any non-measurement command.

Table 10. Mode Status

Status[4:3]

Mode

00

Normal Operation Mode (sleep and cyclic operations)

01

Command Mode

10

Renesas Reserved for Test Mode

11

Renesas Reserved

The I2C interface is compliant with the NXP I2C Bus Specification, Rev. 06 (UM10204, 4 April 2014). All modes up to High

Speed Mode are supported. Slave address codes 04HEX to 07HEX must not be programmed to the ZSSC3230 since they are

exclusively used for the High Speed Mode. The ZS SC3230 will support 7 bit addressing only.

In I2C Mode, each command is started as shown in Figure 15. Only the number of bytes that are needed for the command

must be sent. An exception is the I2C High Speed Mode where 3 bytes must always be sent. After the execution of a

command (busy = 0), the expected data can be read as illustrated in Figure 16 or if no data are returned by the command,

the next command can be sent. The status can be read at any time as described in Figure 17.

S

SlaveAddr

A

0

Command

A P

S

SlaveAddr

0 A

Command

A

CmdDat

<15:8>

A

CmdDat

<7:0>

A P

Command Request (I2C Write)

write

write

from master to slave

from slave to master

S

START condition

P

STOP condition

A

N

acknowledge

not acknowledge

Figure 15. I2C Command Request