SN74ACT1071

10-BIT BUS-TERMINATION ARRAY

WITH BUS-HOLD FUNCTION

SCAS192 – D3994, MARCH 1992 – REVISED APRIL 1993

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

Copyright

© 1993, Texas Instruments Incorporated

4–1

• Designed to Ensure Defined Voltage Levels

on Floating Bus Lines in CMOS Systems

• Reduces Undershoot and Overshoot

Caused By Line Reflections

• Repetitive Peak Forward

Current ...IFRM = 100 mA

• Inputs Are TTL-Voltage Compatible

• Low Power Consumption (Like CMOS)

• ESD Protection Exceeds 2000 V Per

MIL-STD-883C, Method 3015; Exceeds

200 V Using Machine Model

(C = 200 pF, R = 0)

• Center-Pin V

CC and GND Configuration

Minimizes High-Speed Switching Noise

description

This device is designed to terminate bus lines in CMOS systems. The integrated low-impedance diodes clamp

the voltage of undershoots and overshoots caused by line reflections and ensure signal integrity. The device

also contains a bus-hold function that consists of a CMOS-buffer stage with a high-resistance feedback path

between its output and its input. The SN74ACT1071 prevents bus lines from floating without using pullup or

pulldown resistors.

The high-impedance inputs of these internal buffers are connected to the input terminals of the device. The

feedback path on each internal buffer stage keeps a bus line tied to the bus holder at the last valid logic state

generated by an active driver before the bus switches to the high-impedance state.

The SN74ACT1071 is characterized for operation from – 40

°C to 85°C.

logic diagram, one of ten channels (positive logic)

D1

TG

1

VCC

11

VCC

10

GND

3

GND

4

1

2

3

4

5

6

7

14

13

12

11

10

9

8

D1

D2

GND

GND

D3

D4

D5

D10

D9

D8

VCC

VCC

D7

D6

D PACKAGE

(TOP VIEW)

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.