 2000 Infineon Technologies Corp. • Optoelectronics Division • San Jose, CA

Appnote 25

www.infineon.com/opto • 1-888-Infineon (1-888-463-4636)

OSRAM Opto Semiconductors GmbH & Co. OHG • Regensburg, Germany

www.osram-os.com • +49-941-202-7178

2

May 31, 2000-13

Table 1. Electrical inputs

Table 2. Pin description

Operation

In a dot matrix display system, it is advantageous to use a mul-

tiplexed approach with 12 drivers (5 digit plus 7 segments)

rather than 35 segment drivers, reducing the number of drives

and interconnections required. A multiplexed system must be a

synchronous system or the digits or elements may have differ-

ent on (lit) times and therefore varying brightness.

The DLX713X is an internally multiplexed display but the data

entry is asynchronous. Loading data is similar to writing into a

RAM. Present the data, select the chip, and give a write signal.

For a multidigit system, each digit has its own unique location

and will display its contents until replaced by another code.

The waveforms of Figure 4 demonstrates the relationship of

the signals required to generate a write cycle. Check the data

sheet for minimum values required for each signal.

Pin

Name

Pin

Name

14

D6 data input (MSD)

2LT lamp test

13

D5 data input

3CE chip enable

12

D4 data input

4WR write

11

D3 data input

5

BL1 brightness

10

D2 data input

6

BL0 brightness

9

D1 data input

7

GND

8

D0 data input (LSD)

Positive Supply +5 V

GND

Ground

D0–D6

Data Lines, see Figure 3 (Character set)

CE

Chip Enable (active low)

Determines which device in an array will

accept data

WR

Write (active low)

Data and chip enable must be present and

stable before and after the write pulse (see

DLX713X data sheet for timing)

BL0, BL1

Blanking Control Input (active low)

Used to control level of display brightness

LT

Lamp Test (active low)

Causes all dots to light at 1/2 brightness

Figure 3. Character set

Figure 4. Timing characteristics

Display Blanking and Dimming

The DLX713x Intelligent Display has the capability of three

levels of brightness plus blank. Figure 5 shows the combina-

tion of BL0 and BL1 for the different levels of brightness. The

BL0 and BL1 inputs are independent of write and chip enable

and does not affect the contents of the internal memory. A

flashing display can be achieved by pulsing the blanking pins

at a 1–2 hertz rate. Either BL0 or BL1 should be held high to

light up the display.

Table 3. Dimming and blanking control

Brightness Level

BL1

BL0

Blank

0

0

1/7 brightness

0

1

1/2 brightness

1

0

full brightness

1

1

ASCII

CODE

D0

D1

D2

D3

0

0

0

0

0

1

0

0

0

1

0

1

0

0

2

1

1

0

0

3

0

0

1

0

4

1

0

1

0

5

0

1

1

0

6

1

1

1

0

7

0

0

0

1

8

1

0

0

1

9

0

1

0

1

A

1

1

0

1

B

0

0

1

1

C

1

0

1

1

D

0

1

1

1

E

1

1

1

1

F

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

0

1

2

3

4

5

6

7

D6 D5 D4 HEX

1. High=1 level. 2. Low=0 level.

T

W

T

DS

T

CES

CE

WR

D0-D6

T

DH