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ST72F324LJ2T5 Datasheet(PDF) 52 Page - STMicroelectronics

Part # ST72F324LJ2T5
Description  3V range 8-bit MCU with 8 to 32K Flash/ROM, 10-bit ADC, 4 timers, SPI, SCI interface
PDF  154 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ST72F324LJ2T5 Datasheet(HTML) 52 Page - STMicroelectronics

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ST72324Lxx
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MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK (Cont’d)
Bit 0 = OIF Oscillator interrupt flag
This bit is set by hardware and cleared by software
reading the MCCSR register. It indicates when set
that the main oscillator has reached the selected
elapsed time (TB1:0).
0: Timeout not reached
1: Timeout reached
CAUTION: The BRES and BSET instructions
must not be used on the MCCSR register to avoid
unintentionally clearing the OIF bit.
MCC BEEP CONTROL REGISTER (MCCBCR)
Read/Write
Reset Value: 0000 0000 (00h)
Bit 7:2 = Reserved, must be kept cleared.
Bit 1:0 = BC[1:0] Beep control
These 2 bits select the PF1 pin beep capability.
The beep output signal is available in ACTIVE-
HALT mode but has to be disabled to reduce the
consumption.
Table 16. Main Clock Controller Register Map and Reset Values
7
0
0
0
0
0
0
0
BC1
BC0
BC1
BC0
Beep mode with fOSC2=8MHz
0
0
Off
0
1
~2-KHz
Output
Beep signal
~50% duty cycle
1
0
~1-KHz
1
1
~500-Hz
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
002Ch
MCCSR
Reset Value
MCO
0
CP1
0
CP0
0
SMS
0
TB1
0
TB0
0
OIE
0
OIF
0
002Dh
MCCBCR
Reset Value
0
0
0
0
0
0
BC1
0
BC0
0
1



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