INPUT EQUIVALENT CIRCUIT

LOGIC DIAGRAM

PIN DESCRIPTION

PIN No

SYMBOL

NAME AND FUNCT ION

1

CLEAR

Asyncronous Master Reset

(Active LOW)

2, 5, 7, 10,

12, 15

Q0 to Q5

Flip-Flop Outputs

3, 4, 6, 11,

13, 14

D0 to D5

Data Inputs

9

CLOCK

Clock Input (LOW-to-HIGH,

Edge- Triggered)

8

GND

Ground (0V)

16

Positive Supply Voltage

TRUTH TABLE

I NPUTS

OUT PUT S

F UNCTIO N

CL EAR

D

CLO CK

Q

L

X

X

L

CLEAR

HL

L

HH

H

HX

NO CHANGE

X:Don’t Care

Thislogic diagram has notbe used to estimate propagation delays

74VHC174

2/10