A0

A1

A2

INT0

SD0

SC0

INT1

SD1

SC1

GND

VCC

SDA

SCL

INT

SC3

SD3

INT3

SC2

SD2

INT2

VDPU1

VDPU0

VIA to Power Plane

Partial Power Plane

VDPU3

VDPUM

VIA to GND Plane (Inner Layer)

Polygonal

Copper Pour

VCC

GND

Bypass/Decoupling

Capacitors

GND

VDPU2

To I2C Master

LEGEND

21

TCA9544A

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SCPS209C – MAY 2014 – REVISED NOVEMBER 2019

Product Folder Links: TCA9544A

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11 Layout

11.1 Layout Guidelines

For PCB layout of the TCA9544A, common PCB layout practices should be followed but additional concerns

related to high-speed data transfer such as matched impedances and differential pairs are not a concern for I2C

signal speeds. It is common to have a dedicated ground plane on an inner layer of the board and pins that are

connected to ground should have a low-impedance path to the ground plane in the form of wide polygon pours

and multiple vias. By-pass and de-coupling capacitors are commonly used to control the voltage on the VCC pin,

using a larger capacitor to provide additional power in the event of a short power supply glitch and a smaller

capacitor to filter out high-frequency ripple.

In an application where voltage translation is not required, all VDPUX voltages and VCC could be at the same

potential and a single copper plane could connect all of pull-up resistors to the appropriate reference voltage. In

an application where voltage translation is required, VDPUM, VDPU0, VDPU1, VDPU2, and VDPU3 may all be on the

same layer of the board with split planes to isolate different voltage potentials.

To reduce the total I2C bus capacitance added by PCB parasitics, data lines (SCn, SDn and INTn) should be a

short as possible and the widths of the traces should also be minimized (e.g. 5-10 mils depending on copper

weight).

11.2 Layout Example