TLV5580

8BIT, 80 MSPS LOW POWER A/D CONVERTER

SLAS205B − DECEMBER 1998 − REVISED OCTOBER 2003

www.ti.com

17

PRINCIPLE OF OPERATION

DIGITAL OUTPUTS

The output of TLV5580 is a standard binary code. Capacitive loading on the output should be kept as low as

possible (a maximum loading of 10 pF is recommended) to provide best performance. Higher output loading

causes higher dynamic output currents and can increase noise coupling into the device’s analog front end. To

drive higher loads, use an output buffer is recommended.

When clocking output data from TLV5580, it is important to observe its timing relation to CLK. Pipeline ADC

delay is 4.5 clock cycles to which the maximum output propagation delay is added. See Note 6 in the

specification section for more details.

LAYOUT, DECOUPLING AND GROUNDING RULES

It is necessary for any PCB using the TLV5580 to have proper grounding and layout to achieve the stated

performance. Separate analog and digital ground planes that are spliced underneath the device are advisable.

TLV5580 has digital and analog terminals on opposite sides of the package to make proper grounding easier.

Since there is no internal connection between analog and digital grounds, they have to be joined on the PCB.

Joining the digital and analog grounds at a point in close proximity to the TLV5580 is advised.

As for power supplies, separate analog and digital supply terminals are provided on the device (AVDD/DVDD).

The supply to the digital output drivers is kept separate also (DRVDD). Lowering the voltage on this supply from

the nominal 3.3 V to 3 V improves performance because of the lower switching noise caused by the output

buffers.

Due to the high sampling rate and switched-capacitor architecture, TLV5580 generates transients on the supply

and reference lines. Proper decoupling of these lines is essential. Decoupling as shown in the schematic of the

TLV5580 EVM is recommended.