TLV5614EP

2.7V TO 5.5V 12BIT 3 µs QUADRUPLE DIGITALTOANALOG CONVERTER

WITH POWER DOWN

SGLS355 − JUNE 2006

4

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

Terminal Functions

TERMINAL

I/O

DESCRIPTION

NAME

NO.

I/O

DESCRIPTION

AGND

9

Analog ground

AVDD

16

Analog supply

CS

6

I

Chip select. This terminal is active low.

DGND

8

Digital ground

DIN

4

I

Serial data input

DVDD

1

Digital supply

FS

7

I

Frame synchronization. The falling edge of the frame synchronization pulse indicates the start of a serial data frame

shifted out to the TLV5614.

PD

2

I

Power down. Powers down all DACs (overriding their individual power down settings) and all output stages. This

terminal is active low.

LDAC

3

I

Load DAC. When LDAC is high, no DAC output updates occur when the input digital data is read into the serial

interface. The DAC outputs are only updated when LDAC is low.

REFINAB

15

I

Voltage reference input for DAC A and B

REFINCD

10

I

Voltage reference input for DAC C and D

SCLK

5

I

Serial clock input

OUTA

14

O

DAC A

OUTB

13

O

DAC B

OUTC

12

O

DAC C

OUTD

11

O

DAC D

1

10

100

1000

10000

80

90

100

110

120

130

140

150

Wirebond Voiding Fail Mode

Electromigration Fail Mode

Continuous TJ − 5C

Figure 1. Operating Life Derating Chart