S

S

S

1

1

1

1

0

0

0

0

P0

D0

P1

D1

P2

D2

P3

D3

P4

D4

P5

D5

P6

D6

P7

D7

P

P

P

Calibration Byte (55h)

Command with Address Pointer

Register Data (8 LSBs)

S

P

= Start Condition of SMAART Wire Protocol

= Stop Condition of SMAART Wire Protocol

1-bit default delay

for bus direction change.

Driven by TMP104

t

R

t

F

Baud

TYP

Jitter

-

Jitter +

7

TMP104

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SBOS564B – NOVEMBER 2011 – REVISED DECEMBER 2018

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Copyright © 2011–2018, Texas Instruments Incorporated

Feature Description (continued)

7.2.3 SMAART Wire™ Interface Timing Specifications

Figure 6 shows the key timing and jitter considerations for the SMAART wire interface. Table 1 lists the timing

specifications for ensured, reliable operation. During a transaction, the baud rate must remain within ±1% of its

initialization byte value; however, the baud rate can change from transaction to transaction. There is an allowed

delay between each byte transfer of less than 28 ms, which is the bus inactivity timeout check for the TMP104

SMAART wire interface.

Figure 6. SMAART Wire™ Timing Diagram

Table 1. Timing Diagram Definitions

PARAMETER

MIN

MAX

UNIT

Baud

4.8 k

114 k

Bits/s

tR

Clock/data rise time

0.5

%Baud

tF

Clock/data fall time

0.5

%Baud

Jitter

±1

%Baud

7.3 Programming

7.3.1 Communication Protocol

Each communication of the SMAART wire protocol consists of 8-bit words, transferred least significant bit (LSB)

first. Each 8-bit word begins with a Start bit that is logic low, and ends with a Stop bit that is logic high. By using

a Start bit and Stop bit for each 8-bit word, the TMP104 can calibrate each word and maintain synchronous

communication throughout the process. The host commences the communication by sending a Start bit followed

by the calibration byte (55h), allowing the TMP104 to sync to the baud rate of the host, followed by the Stop bit.

Then, another Start bit is sent, followed by the command register byte and a Stop bit. Finally, a third Start bit is

sent followed by the data byte, where master sends data if the instruction is a write command, or the TMP104

breaks the chain and sends data if the instruction is a read command. The process finishes with a Stop bit. The

sequence is shown in Table 2 and Figure 7.

Table 2. Communication Format

Start bit

Calibration

Stop bit

Start bit

Command

byte

Stop bit

Start bit

Data

byte

Stop bit

Figure 7. Generic Communication BitStream

The TMP104 has two dedicated pins for communication: TX and RX. Usually, these two pins are connected

internally and the signal on the RX propagates to the TX; that is, the TMP104 works in a transparent mode. The

TMP104 breaks this buffer configuration only when it must send data on the bus or during address assignment

and alert procedures.