TPIC44H01DA datasheet(8/31 Pages) TI2

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TPIC44H01

4-CHANNEL SERIAL AND PARALLEL HIGH-SIDE PRE-FET DRIVER

SLIS088 – SEPTEMBER 1998

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

switching characteristics, VCC = 5 V, V(PWR) = 12 V, TC = 25°C

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

t(STG)

Short-to-ground deglitch time

µs

t(OC)

Over-current deglitch time

SDI bits DG1–3 = 0 (default after POR),

120

µs

t(OL)

Open-load deglitch time

(),

See Figures 11, 12, and 17 and Table 4

120

µs

t(retry)

Auto-retry time

tPLH

Propagation turn-on delay, CS or IN1 – 4 to

GATE1 – 4

CG = 400 pF See Figures 1 and 2

µs

tPHL

Propagation turn-off delay, CS or IN1 – 4 to

GATE1 – 4

CG = 400 pF, See Figures 1 and 2

µs

f(SCLK)

Serial clock frequency

t(WH)= t(WL) = 0.5/f(SCLK), See Figure 5

MHz

tsu(lead)

Setup from the falling edge of CS to the

rising edge of SCLK

See Figure 5

100

tsu(lag)

Setup from the falling edge of SCLK to

rising edge of CS

See Figure 5

100

tpd(SDOEN)

Propagation delay from falling edge of CS

to SDO valid

tpd(valid)

Propagation delay from falling edge of

SCLK to SDO valid

RL = 10 kΩ, CL = 200 pF, See Figure 5

tpd(SDODIS)

Propagation delay from rising edge of CS

to SDO Hi-Z state

150

tf(FLT)

Fall time of FLT output

RL = 10 kΩ, CL = 200 pF, See Figure 3

t(active)

POR-to-active status delay, sleep-to-active

status delay

See Figure 4

512

µs

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