RESET

GND

TPS3847

RST

Microprocessor

V(VCC)

47 k:

V(VCC)

TPS3847

www.ti.com

SBVS231A – AUGUST 2014 – REVISED MARCH 2015

Typical Application (continued)

8.2.1.2 Driving Bidirectional Reset Pins

Some microcontrollers have bidirectional reset pins that act as both an input and an output. When using

bidirectional reset pins, place a series resistor between the TPS3847 RESET pin and the microcontroller in order

to protect against excessive current flow in case both the TPS3847 and the microcontroller attempt to drive the

reset line simultaneously. Figure 16 illustrates the connection of the TPS3847 to a microcontroller using a series

resistor to drive a bidirectional reset line. Assuming the maximum voltage that the microprocessor outputs is the

same as the TPS3847 (4 V), use a resistor value greater than 20 k

Ω in order to limit the output current to 2 mA

or less when one pin is driven high and the other is driven low. In order to cover the majority of applications, use

a resistor value of 47 k

Ω.

Figure 16. Connection to Bidirectional Reset Pin

8.2.1.3 Manual Reset (MR) Input

The manual reset (MR) input allows a processor, or other logic devices, to initiate a reset. A logic low on MR

causes RESET to transition to logic low. After MR returns to a logic high and V(VCC) is greater than VIT+, RESET

transitions to a logic high after the reset delay time, td, elapses.

Note that internal to the device MR is connected to a very small current source that goes from the internal sub-

regulated voltage to the MR node. If the logic signal driving MR does not exceed 3 V, there is 25 nA of additional

current drawn from the input supply because of this current source. Do not leave this pin floating; either drive this

pin above or below the MR high and low input levels. Tie MR directly to VCC if not used.

8.2.1.4 Threshold Overdrive

Threshold overdrive is how much V(VCC) exceeds the specified threshold, and is important to know because the

smaller the overdrive, the slower the RESET response. Threshold overdrive is calculated as a percent of the

threshold in question, as shown in Equation 1:

Overdrive = |(V(VCC) / VIT – 1) × 100%|

where:

•

VIT is either VIT– or VIT+, depending on whether calculating the overdrive for the negative-going threshold or the

positive-going threshold, respectively.

(1)

Figure 12 illustrates the VCC minimum detectable pulse versus overdrive, and is used to visualize the

relationship overdrive has on tpd(VCC) for negative-going events.

For positive-going events, after the overdrive is greater than 5%, the changes to td are negligible because of the

significantly longer delay time. When overdrive is less than 5%, td can increase to 200 ms while the device waits

for the next voltage reference refresh pulse.

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