V

A

AGND

To Internal Circuitry

I/O

11

ADC14155QML-SP

www.ti.com

SNAS378L – NOVEMBER 2008 – REVISED FEBRUARY 2019

Product Folder Links: ADC14155QML-SP

Submit Documentation Feedback

Copyright © 2008–2019, Texas Instruments Incorporated

(1)

Pre and post irradiation limits are identical to those listed in the Electrical Characteristics tables. Radiation testing is performed per MIL-

STD-883, Test Method 1019.

(2)

The inputs are protected as shown below. Input voltage magnitudes above VA or below GND will not damage this device, provided

current is limited per Note 5. However, errors in the A/D conversion can occur if the input goes above 2.6 V or below GND as described

in the Recommended Operating Conditions section.

(3)

To ensure accuracy, it is required that |VA – VD| ≤ 100 mV and separate bypass capacitors are used at each power supply pin.

(4)

With the test condition for VREF = 1 V (2-VP-P differential input), the 14-bit LSB is 122.1 µV.

(5)

When the input voltage at any pin exceeds the power supplies (that is, VIN < AGND, or VIN > VA), the current at that pin should be

limited to ±5 mA. The ±50 mA maximum package input current rating limits the number of pins that can safely exceed the power

supplies with an input current of ±5 mA to 10.

(6)

Typical figures are at TA = 25°C and represent most likely parametric norms at the time of product characterization. The typical

specifications are not ensured.

(7)

Specified by design.

(8)

Specified by characterization.

6.8 ADC14155 Converter Electrical Characteristics (Continued) Timing and AC

Characteristics

(1)

Unless otherwise specified, the following specifications apply: AGND = DGND = DRGND = 0 V, VA = VD = 3.3 V, VDR = 1.8 V,

Internal VREF = 1 V, fCLK = 155 MHz, VCM = VRM, CL = 5 pF/pin, Differential Analog Input, Single-Ended Clock Mode, Offset

Binary Format. Typical values are for TA = 25°C. Timing measurements are taken at 50% of the signal amplitude. Boldface

limits apply for TMIN ≤ TA ≤ TMAX. All other limits apply for TA = 25°C

(2) (3) (4) (5)

PARAMETER

TEST CONDITIONS

NOTES

TYP(6)

MIN

MAX

UNITS

SUB-

GROUPS

Maximum clock frequency

155

MHz

[7, 8A, 8B]

Minimum clock frequency

5

MHz

Clock high time

3.0

ns

Clock low time

3.0

ns

Conversion latency

See(7)

8

Clock

cycles

[4, 5, 6]

tOD

Output delay of CLK to

DATA

Relative to falling edge of CLK

2.0

ns

tSU

Data output setup time

Relative to DRDY

See(8)

2.1

1.22

ns

tH

Data output hold time

Relative to DRDY

See(8)

2.1

1.83

ns

tAD

Aperture delay

0.5

ns

tAJ

Aperture jitter

0.08

ps rms

Power down recovery time

0.1 µF to GND on pins 43, 44;

10 µF and 0.1 µF between

pins 43, 44; 0.1 µF and 10 µF

to GND on pins 47, 48

3.0

ms