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CS

CONVST

SDO

D15

1

16

17

18

19

SCLK

LSB

BUSY

D0

D14

D13

Conversion N+1

D12

D1

D0

D0

th6

tsu7

tcyc

tsu6

tw3

td15

MSB of Conversion N−1

MSB of Conversion N

td13

td7

th8

tsu3

D15 Repeated

No FS

Fall

Zone

FS Fall After This

Point Reads Data

From Conversion

N

FS Fall Before This

Point Reads Data

From Conversion

N−1

If There is 19th SCLK

Conversion N

tquiet2

tquiet1

FS

tquiet3

2

3

4

Don’t Care

(D0 Repeated)

PRINCIPLES OF OPERATION

REFERENCE

ADS8370

SLAS450 – JUNE 2005

Figure 47. Read Frame Controlled via FS (FS is High When BUSY Falls)

If another data frame is attempted by pulling up FS during an active data frame, then the ongoing frame is

aborted and a new frame is started.

The ADS8370 is a high-speed successive approximation register (SAR) analog-to-digital converter (ADC). The

architecture is based on charge redistribution, which inherently includes a sample/hold function.

The device includes a built-in conversion clock, internal reference, and 40-MHz SPI compatible serial interface.

The maximum conversion time is 1.16

µs which is capable of sustaining a 600-kHz throughput.

The analog input is provided to the two input pins: +IN and –IN. When a conversion is initiated, the differential

input on these pins is sampled on the internal capacitor array. While a conversion is in progress, both inputs are

disconnected from any internal function.

The ADS8370 has a built-in 4.096-V (nominal value) reference but can operate with an external reference also.

When the internal reference is used, pin 9 (REFOUT) should be shorted to pin 8 (REFIN) and a 0.1-µF

decoupling capacitor and a 1-µF storage capacitor must be connected between pin 8 (REFIN) and pin 7 (REFM)

(see Figure 48). The internal reference of the converter is buffered.

20

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