CDx4HC(T)259 High-Speed SMOS Logic 8-Bit Addressable Latch

1 Features

• Buffered inputs and outputs

• Four operating modes

• Typical propagation delay of 15ns at VCC = 5V, CL

= 15pF, TA = 25oC

• Fanout (over temperature range)

– Standard Outputs: 10 LSTTL loads

– Bus driver outputs: 15 LSTTL loads

• Wide operating temperature range: -55oC to 125oC

• Balanced propagation delay and transition times

• Significant power reduction compared to LSTTL

logic ICs

• HC types

– 2 V to 6 V operation

– High noise immunity: NIL = 30%, NIH = 30% of

VCC at VCC = 5 V

• HCT types

– 4.5 V to 5.5 V operation

– Direct LSTTL input logic compatability, VIL = 0.8

V (max), VIH = 2 V (min)

– CMOS input compatibility, II ≤ 1µA at VOL, VOH

2 Description

The CDx4HC(T)259 is an 8-bit addressable latch with

three active modes of operation (addressable latch,

memory, 8-line demultiplexer) and one reset mode.

Device Information

PART NUMBER

PACKAGE

(1)

BODY SIZE (NOM)

CD54HC259F3A

CDIP (16)

21.34 mm × 6.92 mm

CD54HCT259F3A

CDIP (16)

21.34 mm × 6.92 mm

CD74HC259E

PDIP (16)

19.31 mm × 6.35 mm

CD74HCT259E

PDIP (16)

19.31 mm × 6.35 mm

CD74HC259M

SOIC (16)

9.90 mm × 3.90 mm

CD74HCT259M

SOIC (16)

9.90 mm × 3.90 mm

(1)

For all packages see the orderable addendum at the end of

the data sheet.

S0

S1

S2

CLR

G

3:8 DECODER

001

010

011

100

101

110

111

D

LE

Q

R

D

LE

Q

R

D

LE

Q

R

D

LE

Q

R

D

LE

Q

R

D

LE

Q

R

D

LE

Q

R

D

LE

Q

R

Q7

Q6

Q5

Q4

Q3

Q2

Q1

Q0

LATCH

ENABLE

D

OUTPUT STORAGE

000

Functional Block Diagram

CD54HC259, CD74HC259, CD54HCT259, CD74HCT259

SCHS173D – NOVEMBER 1997 – REVISED NOVEMBER 2021

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.