IMX2378F datasheet(13/36 Pages) POWERINT

13 / 36 page

Rev. D 12/24

InnoMux2-EP

www.power.com

The default refresh time is T

REFRESH, which is doubled to 2 × TREFRESH

during start-up. The longer the refresh time the better, but the

MOSFET needs to be turned back on before the end of the primary

on time. Once the CV outputs are in regulation the refresh time is

reduced to T

REFRESH. Because the output is no longer changing, the

refresh is only needed to top up CDR and by reducing the refresh

time the risk of the primary on time finishing before the refresh is

reduced.

A diode is required to be placed between the gate-source of each

selection MOSFET to provide a path for charging the capacitor. A low

forward voltage diode such as a Schottky diode should be used.

The optimal capacitor value for CDR depends on the gate charge of

the selection MOSFET. The selection MOSFET on-level gate voltage is

determined by V

BPS × (CDR/(CG + CDR), so it is essential that the gate

charge (at 5 V gate voltage) is much smaller than the charge in the

CDR capacitor. A typical value for the CDR capacitor is 100 nF. For

higher CDR capacitor values, the refresh time might be insufficient

and the capacitor will not be able to follow the output during start-up.

It is therefore important to select low gate-charge devices for the

selection MOSFETs to minimise the required CDR capacitor value as

well as to minimise energy required to drive the MOSFETs.

High-Side MOSFET Static Pull-Down

To ensure that the selection MOSFET gates are held low when the

secondary is not in control, the CDR1 and CDR2 pins have an internal

pull down circuit “ON” feature to pull the pin low and reduce any

voltage on the gate due to capacitive coupling.

Synchronous Rectifier Driver

The SR driver on the InnoMux2-EP IC is not an “on/off” driver. The

SR MOSFET’s gate-source voltage is modulated to regulate the

FORWARD pin voltage to roughly -40 mV while the discharge current

is flowing in the SR MOSFET. The regulated approach allows for

improved noise immunity, removing the possibility of the MOSFET

being turned off too early causing increased power loss.

A force-on signal provides a boost when turning on the SR MOSFET

to charge the gate-source capacitance quickly. A force off signal is

used to quickly discharge the gate-source capacitance when operating

in CCM and also ensure the MOSFET is held off when the secondary is

not conducting.

FWD

GND

Force Off

Force On

PI-9706-031423

Figure 13. Synchronous Rectifier Driver Diagram.

For optimum performance, an SR MOSFET with a gate-source

capacitance of less than 10 nF is recommended.

SR Disable Protection

In each cycle the SR is only engaged if a new cycle is requested by

the secondary controller and the negative edge is detected on the

FORWARD pin.

SR Static Pull-Down

To ensure that the SR gate is held low when the secondary is not in

control, the SYNCHRONOUS RECTIFIER DRIVE pin has internal pull

down circuit “ON” device to pull the pin low and reduce any voltage

on the SR gate due to capacitive coupling from the FORWARD pin.

Short/Open SR Protection

In order to protect against the SYNCHRONOUS RECTIFIER DRIVE pin

system faults, (an SR pin short to ground or SR pin open), the

secondary controller has a protection mode that ensures that the

SYNCHRONOUS RECTIFIER DRIVE pin is connected to an external

FET. If the external capacitance on the SYNCHRONOUS RECTIFIER

DRIVE pin is less than 200 pF, the device will assume that the

SYNCHRONOUS RECTIFIER DRIVE pin is “open”. If the external

capacitance on the SYNCHRONOUS RECTIFIER DRIVE pin is above

20 nF, the device will assume the SYNCHRONOUS RECTIFIER DRIVE

pin is “short”. In either of these two cases a fault is detected

otherwise the controller will assume an SR FET is connected.

In the event SYNCHRONOUS RECTIFIER DRIVE pin fault is detected

the secondary controller will stop requesting pulses from the primary

and initiate auto-restart.

Multi-Output Control

The multi-output control regulates each output independently by

requesting pulses from the primary based on the FB pin voltages of

each output. The transformer energy is then directed to the output

that needs the energy on a cycle-by-cycle basis. This is accomplished

by turning on the appropriate selection MOSFET in series with either

the CV1 or the CV2 output. The transformer shall be designed such

that the V

OR increases between VCV1 and VCV2 and between VCVHV/VLED.

This guarantees that the current through the V

LED diode is negligible

when the selection MOSFET for either V

CV1 or VCV2 is turned on,

disabling both MOSFETs will direct the energy delivery to the LED

output.

InnoMux2-EP Enhanced Audible Noise Reduction

The InnoMux2-EP IC has enhanced features for audible noise

reduction.

Multi-output control can create sub-harmonic frequencies of the

switching frequency in the flux of the transformer. These sub-

harmonics can fall in the audible range. THE InnoMux2-EP IC avoids

such conditions by sharing fractions of discharge pulses between

outputs.

This is achieved by allowing the first part of the discharge pulse to

the V

CVHV/VLED output and then turning on the selection MOSFET part

way through the discharge and allowing the second part of the

discharge to flow via the V

CV1 or VCV2 output. The point at which the

MOSFET is turned on to switch over from the L

ED/CVHV output to the

CV1 or CV2 output is dependent on the relative loading of the

outputs.

This provides an added benefit of reducing the RMS currents in the

secondary windings, reducing power loss. The operating frequency of

each output is increased (while the power switch frequency remains

the same) reducing the output ripple for a given filter capacitance.

IMX2378F Datasheet(PDF) 13 Page - Power Integrations, Inc.

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