UCC15701SLASH2 datasheet(6/23 Pages) TI2

6 / 23 page

UCC15701/2

UCC25701/2

UCC35701/2

Output Inhibit

During normal operation, OUT is driven high at the start

of a clock period and is driven low by voltages on CT, FB

or VSCLAMP.

The following conditions cause the output to be immedi-

ately driven low until a clock period starts where none of

the conditions are true:

1. ILIM > 0.2V

2. FB or SS is less than 0.8V

Current Limiting

ILIM is monitored by two internal comparators. The cur-

rent limit comparator threshold is 0.2V. If the current limit

comparator is triggered, OUT is immediately driven low

and held low for the remainder of the clock cycle, provid-

ing pulse-by-pulse over-current control for excessive

loads. This comparator also causes CF to be charged for

the remainder of the clock cycle.

If repetitive cycles are terminated by the current limit

comparator causing COUNT to rise above 4V, the shut-

down latch is set. The COUNT integration delay feature

will be bypassed by the shutdown comparator which has

a 0.6V threshold. The shutdown comparator immediately

sets the shutdown latch. RF in parallel with CF resets the

COUNT integrator following transient faults. RF must be

greater than (4

· R4) · (1–DMAX).

Latched Shutdown

If ILIM rises above 0.6V, or COUNT rises to 4V, the shut-

down latch will be set. This will force OUT low, discharge

SS and COUNT, and reduce IDD to approximately

750

mA. When, and if, VDD falls below the UVLO stop

threshold, the shutdown latch will reset and IDD will fall

to 130

mA, allowing the circuit to restart. If VDD remains

above the UVLO stop threshold (within the UVLO band),

an alternate restart will occur if VFF is momentarily re-

duced below 1V. External shutdown commands from any

source may be added into either the COUNT or ILIM

pins.

Voltage Feedforward

The voltage slope on CT is proportional to line voltage

over a 4:1 range and equals 2

·VFF (RT·CT). The capac-

itor charging current is set by the voltage across RT.

V(RT) tracks VFF over a range of 0.8V to 3.2V. A chang-

ing line voltage will immediately change the slope of

V(CT), changing the pulse width in a proportional manner

without using the feedback loop, providing excellent dy-

namic line regulation.

VFF is intended to operate accurately over a 4:1 range

between 0.8V and 3.2V. Voltages at VFF below 0.6V or

above 4.0V will initiate a soft stop cycle and a chip restart

when the under/over voltage condition is removed.

Volt-Second Clamp

A constant volt-second clamp is formed by comparing the

timing capacitor ramp voltage to a fixed voltage derived

from the reference. Resistors R4 and R5 set the

volt-second limit. For a volt-second product defined as

VIN

tON(max), the required voltage at VSCLAMP is:

()

÷ ··

max

The duty cycle limit is then:

VS CLAMP

VFF

,or

VS CLAMP

IN ·

The

maximum

duty

cycle

realized

when

the

feedforward voltage is set at the low end of the operating

range (VFF = 0.8V).

The absolute maximum duty cycle is:

MAX

VS CLAMP

REF

Frequency Set

The frequency is set by a resistor from RT to ground and

a capacitor from CT to ground. The frequency is approxi-

mately:

()

External synchronization is via the SYNC pin. The pin

has a 1.5V threshold , making it compatible with 5V and

3.3V CMOS logic. The input is level sensitive, with a high

input forcing the oscillator ramp low and the output low.

An active pull down on the SYNC pin allows it to be un-

connected when not used.

Gate Drive Output

The UCC35701/2 is capable of a 1A peak output current.

Bypass with at least 0.1

mF directly to PGND. The capac-

itor must have a low equivalent series resistance and in-

ductance. The connection from OUT to the power

MOSFET gate should have a 2

W or greater damping re-

sistor and the distance between chip and MOSFET

should be minimized. A low impedance path must be es-

tablished between the MOSFET source (or ground side

of the current sense resistor), the VDD capacitor and

PGND. PGND should then be connected by a single path

(shown as RGND) to GND.

APPLICATION INFORMATION (cont.)

UCC15701/2 Datasheet(PDF) 6 Page - Texas Instruments

UCC15701/2 Datasheet(HTML) 6 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

Datasheet Download

Link URL