ZL40262

DS20006788A-page 4

 2024 Microchip Technology Inc.

List of Figures

FIGURE 0-1: “Functional Block Diagram.”..................................................................................... 1

FIGURE 1-1: “20-Lead 4 mm x 4 mm VQFN Pin Diagram.”........................................................... 6

FIGURE 2-1: “Input driven by source terminated HCSL.” ............................................................ 9

FIGURE 2-2: “Input driven by receiver terminated HCSL.” ........................................................ 10

FIGURE 2-3: “Input driven by AC-coupled LVPECL output.”..................................................... 10

FIGURE 2-4: “Input driven by AC-coupled LVDS.” ..................................................................... 10

FIGURE 2-5: “Input driven by a single-ended output.”............................................................... 11

FIGURE 2-6: “Source-terminated HCSL.” .................................................................................... 11

FIGURE 2-7: “Receiver-terminated HCSL.”.................................................................................. 11

FIGURE 2-8: “Power Supply Filtering.” ........................................................................................ 13

FIGURE 2-9: “100 MHz HCSL Phase Noise.” ............................................................................... 13

FIGURE 2-10: “133 MHz HCSL Phase Noise.” ............................................................................. 14

FIGURE 2-11: “400 MHz HCSL Phase Noise.” ............................................................................. 14

FIGURE 2-12: “491.52 MHz HCSL Phase Noise.” ........................................................................ 15

FIGURE 3-1: “Single-Ended Measurement Points for Absolute Cross Point and Swing.” ..... 24

FIGURE 3-2: “Single-Ended Measurement Points for Delta Cross Point.” ............................... 24

FIGURE 3-3: “Single-Ended Measurement Points for Rise and Fall Time Matching.”............. 24

FIGURE 3-4: “Differential Measurement Points for Rise and Fall Time.”.................................. 25

FIGURE 3-5: “Differential Measurement Points for Ringback.” ................................................. 25

FIGURE 3-6: “PCIe Test Circuit.” .................................................................................................. 25

4.1 “Package Marking Information”.............................................................................................. 27

“20-Lead 4 mm × 4 mm VQFN with 2.125 mm Exposed Pad (LWC) Package Outline and Rec-

ommended Landing Pattern”.......................................................................................... 28