CLKP

Control

Logic

/OE

CLKAP

CLKBP

SEL

6 MO

6 MO

VDD

CLKN

CLKAN

CLKBN

D1P

DA1P

DB1P

D1N

DA1N

DB1N

D2P

DA2P

DB2P

D2N

DA2N

DB2N

D3P

DA3P

DB3P

D3N

DA3N

DB3N

D4P

DA4P

DB4P

D4N

DA4N

DB4N

GND

Copyright © 2018, Texas Instruments Incorporated

16

TS5MP645

SCDS385B – JANUARY 2018 – REVISED JULY 2018

www.ti.com

Product Folder Links: TS5MP645

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Copyright © 2018, Texas Instruments Incorporated

8 Detailed Description

8.1 Overview

The TS5MP645 is a high-speed 4 Data lane 2:1 MIPI Switch. The device includes 10 channels (5 differential)

with 4 differential data lanes and 1 differential clock lane for D-PHY, CSI or DSI. The switch allows a single MIPI

port to interface between two MIPI modules, expanding the number of potential MIPI devices that can be used

within a system that is MIPI port limited.

8.2 Functional Block Diagram