TSC2102IDA datasheet(24/58 Pages) TI2

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TSC2102

SLAS379A− APRIL 2003 − REVISED JUNE 2004

www.ti.com

STEREO AUDIO DAC

The TSC2102 includes a stereo audio DAC, which can operate with a maximum sampling rate of 48 kHz and can support

all standard audio rates of 8 kHz, 11.025 kHz, 12 kHz, 16kHz, 22.05 kHz, 24 kHz, 32 kHz, 44.1 kHz, and 48 kHz.

When the DAC is operating, the TSC2102 requires an audio MCLK input applied. The user is required to set D13 of control

off the MCLK and BCLK, and the internal oscillator is powered down to save power.

Each channel of the stereo audio DAC consists of a digital audio processing block, a digital interpolation filter, digital

delta-sigma modulator, and analog reconstruction filter. The DAC is designed to provide enhanced performance at low

sample rates through increased oversampling and image filtering, thereby keeping quantization noise generated within the

delta-sigma modulator and signal images strongly suppressed within the audio band to beyond 20 kHz. This is realized

by keeping the upsampled rate constant at 128 x Fsref and changing the oversampling ratio as the input sample rate is

changed. For Fsref of 48 kHz, the digital delta-sigma modulator always operates at a rate of 6.144 MHz. This ensures that

quantization noise generated within the delta-sigma modulator stays low within the frequency band below 20 kHz at all

sample rates. Similarly, for Fsref rate of 44.1 kHz, the digital delta-sigma modulator always operates at a rate of 5.6448

MHz.

PLL

The TSC2102 has an on chip PLL to generate the needed internal audio clocks from the clock available in the system. The

PLL supports a MCLK varying from 2 MHz to 50 MHz and is register programmable to enable generation of the required

sampling rates from a wide range of system clocks.

The DAC sampling rate is given by:

DAC_FS = Fsref/N

where, Fsref is 44.1 kHz or 48 kHz and N =1, 1.5, 2, 3, 4, 5, 6 are register programmable.

The PLL can be enabled or disabled using register programmability.

D When PLL is disabled

Fsref

+ MCLK

128

Q = 2, 3

…17

D When PLL is enabled

Fsref

+ MCLK

2048

P = 1, 2, 3,

…, 8

K = J.D

J = 1, 2, 3,

….,64

D = 0, 1, 2,

…, 9999

where, D is the 4-digit fractional part of K with lagging zeros (e.g. if K = 8.5, then D = 5000 and if K = 8.02, then D = 200).

P, J and D are register programmable.

D When D = 0, the following condition needs to be satisfied

2MHz

v MCLK

v 20 MHz

D When D ≠ 0, the following condition needs to be satisfied

10 MHz

v MCLK

v 20 MHz

Example 1:

For MCLK = 12 MHz and Fsref = 44.1 kHz

P = 1, K = 7.5264

⇒ J = 7, D = 5264

TSC2102IDA Datasheet(PDF) 24 Page - Texas Instruments

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