ADC12DL040

SNAS250D – FEBRUARY 2005 – REVISED APRIL 2013

www.ti.com

FUNCTIONAL DESCRIPTION

Operating on a single +3.0V supply, the ADC12DL040 uses a pipeline architecture and has error correction

circuitry to help ensure maximum performance. The differential analog input signal is digitized to 12 bits. The

user has the choice of using an internal 1.0 Volt or 0.5 Volt stable reference, or using an external reference. Any

external reference is buffered on-chip to ease the task of driving that pin.

The output word rate is the same as the clock frequency, which can be between 10 MSPS and 40 MSPS

(typical) with fully specified performance at 40 MSPS. The analog input for both channels is acquired at the rising

edge of the clock and the digital data for a given sample is delayed by the pipeline for 7 clock cycles. Duty cycle

stablization and output data format are selectable using the quad state function DF/DCS pin. The output data can

be set for offset binary or two's complement.

A logic high on the power down (PD) pin reduces the converter power consumption to 36 mW.

Applications Information

OPERATING CONDITIONS

We recommend that the following conditions be observed for operation of the ADC12DL040:

2.7V

≤ VA ≤ 3.6V

VD = VA

2.4V

≤ VDR ≤ VA

10 MHz

≤ fCLK ≤ 40 MHz

0.8V

≤ VREF ≤ 1.2V (for an external reference)

0.5V

≤ VCM ≤ 2.0V

Analog Inputs

There is one reference input pin, VREF, which is used to select an internal reference, or to supply an external

reference. The ADC12DL040 has two analog signal input pairs, VIN A+ and VIN A- for one converter and VIN B+

and VIN B- for the other converter. Each pair of pins forms a differential input pair.

Reference Pins

The ADC12DL040 is designed to operate with an internal 1.0V or 0.5V reference, or an external 1.0V reference,

but performs well with external reference voltages in the range of 0.8V to 1.2V. Lower reference voltages will

decrease the signal-to-noise ratio (SNR) of the ADC12DL040. Increasing the reference voltage (and the input

signal swing) beyond 1.2V may degrade THD for a full-scale input, especially at higher input frequencies.

It is important that all grounds associated with the reference voltage and the analog input signal make connection

to the ground plane at a single, quiet point to minimize the effects of noise currents in the ground path.

The six Reference Bypass Pins (VRPA, VRMA, VRNA, VRPB, VRMB and VRNB) are made available for bypass

purposes. All these pins should each be bypassed to ground with a 0.1 µF capacitor. A 10 µF capacitor should

be placed between the VRPA and VRNA pins and between the VRPB and VRNB pins, as shown in Figure 37. This

configuration is necessary to avoid reference oscillation, which could result in reduced SFDR and/or SNR.

Smaller capacitor values than those specified will allow faster recovery from the power down mode, but may

result in degraded noise performance. Loading any of these pins other than VRMA and VRMB may result in

performance degradation.

The nominal voltages for the reference bypass pins are as follows:

VRM = 1.5 V

VRP = VRM + VREF / 2

VRN = VRM − VREF / 2

20

Submit Documentation Feedback

Copyright © 2005–2013, Texas Instruments Incorporated

Product Folder Links: ADC12DL040