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CSD86336Q3D

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SLPS666 – MARCH 2018

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Copyright © 2018, Texas Instruments Incorporated

Application Information (continued)

Table 1 compares the traditional DC measured RDS(ON) of CSD86336Q3D versus its ZDS(ON). This comparison

takes into account the improved efficiency associated with TI’s patented packaging technology. As such, when

comparing TI’s power block products to individually packaged discrete MOSFETs or dual MOSFETs in a

standard package, the in-circuit switching performance of the solution must be considered. In this example,

individually packaged discrete MOSFETs or dual MOSFETs in a standard package would need to have DC

measured RDS(ON) values that are equivalent to the ZDS(ON) value of CSD86336Q3D in order to have the same

efficiency performance at full load. Mid to light-load efficiency will still be lower with individually packaged discrete

MOSFETs or dual MOSFETs in a standard package.

Table 1. Comparison of RDS(ON) vs ZDS(ON)

PARAMETER

HS

LS

TYP

MAX

TYP

MAX

Effective AC on-impedance ZDS(ON) (VGS = 5 V)

9.1

—

3.4

—

DC measured RDS(ON) (VGS = 4.5 V)

9.1

11.4

4.6

5.7

The CSD86336Q3D NexFET™ power block is an optimized design for synchronous buck applications using 5-V

gate drive. The control FET and sync FET silicon are parametrically tuned to yield the lowest power loss and

highest system efficiency. As a result, a new rating method is needed which is tailored towards a more systems-

centric environment. System-level performance curves such as power loss, safe operating area (SOA), and

normalized graphs allow engineers to predict the product performance in the actual application.

6.2 Power Loss Curves

MOSFET centric parameters such as RDS(ON) and Qgd are needed to estimate the loss generated by the devices.

In an effort to simplify the design process for engineers, Texas Instruments has provided measured power loss

performance curves. Figure 1 plots the power loss of the CSD86336Q3D as a function of load current. This curve

is measured by configuring and running the CSD86336Q3D as it would be in the final application (see

Figure 30). The measured power loss is the CSD86336Q3D loss and consists of both input conversion loss and

gate drive loss. Equation 1 is used to generate the power loss curve.

(VIN × IIN) + (VDD × IDD) – (VSW_AVG × IOUT) = power loss

(1)

The power loss curve in Figure 1 is measured at the maximum recommended junction temperatures of 125°C

under isothermal test conditions.

6.3 Safe Operating Area (SOA) Curves

The SOA curve in the CSD86336Q3D data sheet provides guidance on the temperature boundaries within an

operating system by incorporating the thermal resistance and system power loss. Figure 3 outlines the

temperature conditions required for a given load current. The area under the curve dictates the safe operating

area. All the curves are based on measurements made on a PCB design with dimensions of 4 in (W) × 3.5 in (L)

× 0.062 in (T) and 6 copper layers of 1-oz copper thickness.

6.4 Normalized Curves

The normalized curves in the CSD86336Q3D data sheet provides guidance on the power loss and SOA

adjustments based on their application specific needs. These curves show how the power loss and SOA

boundaries will adjust for a given set of systems conditions. The primary Y-axis is the normalized change in

power loss and the secondary Y-axis is the change in system temperature required in order to comply with the

SOA curve. The change in power loss is a multiplier for the power loss curve and the change in temperature is

subtracted from the SOA curve.