LM27213MTDXSLASHNOPB.B datasheet(3/38 Pages) TI2

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LM27213

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SNVS377A – FEBRUARY 2006 – REVISED MARCH 2013

PIN DESCRIPTIONS (TSSOP/LLP)

Name

Description

CBOOT

Connection for the high-side drive bootstrap capacitor

High-side FET gate drive output

Connect to switch node (drain of bottom power FET) to detect inductor current reversal. Also

serves as the return path for the high-side FET gate drive currents

No connect

SRCK

Source Kelvin. Connect directly to source of low-side FET to detect negative inductor current

No connect

Over-current sense. Voltage between this pin and the regulator output is the voltage across

ILIM

the current sense resistor

Current limit reference. Voltage between this pin and the regulator output sets the inductor

ILIMREF

current limit level

Current sense. Voltage between this pin and the regulator output sets the cycle by cycle

CMP

inductor current

Inductor current reference. Voltage between this pin and the regulator output programs the

CMPREF

inductor current

VREF

Desired regulator output voltage under no load

Signal to start clock chip PLL locking. A low level indicates that the core supply is now stable

CLK_EN#

and the CPU can begin clocking

DGND

Digital ground

Power good flag. Open-drain output. Logic high when output voltage enters the power good

PGOOD

window and XPOK is asserted. Masked during transitions

Input that tells the LM27213 that the supply voltage for the Memory Controller Hub is up. The

XPOK

LM27213 will regulate the output voltage to VBOOT until XPOK transitions to a high state.

PGOOD is forced low as long as this pin is low

SENSE

Regulator output voltage sense. Connect directly to output

Over-voltage protection level. Connect this pin to the desired reference voltage to set the

VOVP

trigger level for over-voltage protection

P_Z2

Factory reference trim, do not connect. This pin must float

P_Z1

Factory reference trim, do not connect. This pin must float

No connect

P_Z0

Factory reference trim, do not connect. This pin must float

SGND

Signal Ground

VDD

Chip power supply

Soft start, soft shutdown and slew rate control. Connect a capacitor between this pin and

ground to control the soft start and soft shutdown speed. The value of the capacitor will also

define the slew rate of the dynamic VID transitions

VIR7

1.7V reference voltage

Initial output voltage desired after soft start completes. Connect this pin to the desired

VBOOT

reference level

VSLP

Desired Voltage in Sleep Mode. Connect this pin to the desired reference level

No connect

VDAC

Buffered Digital-to-Analog converter output

VSTP

Desired output voltage in Stop CPU mode. Connect this pin to the desired reference level

SLP

When this pin is logic high, VREF voltage is equal to that on the VSLP pin

STP_CPU#

When this pin is logic low, VREF voltage is equal to that on the VSTP pin

DE_EN#

Power saving mode trigger signal. Enables diode emulation

VID5

6th and most significant bit to program the output voltage

VID4

5th bit to program the output voltage

VID3

4th bit to program the output voltage

VID2

3rd bit to program the output voltage

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