LMH0318RTWR datasheet(13/59 Pages) TI2

13 / 59 page

OUT1(100

)

VCO

CDR

Raw

Retimed

Eye

Monitor

Loss Of

Signal

FR4 EQ

Loss Of

Signal

OUT0(75

)

Mux Control

Clock

Mute

Control Logic Block

Status

100

FPGA/Cross Point

100

FPGA/Cross Point

100

Data or Clock

BNC

Polarity Control

LMH0318

www.ti.com

SNLS508 – SEPTEMBER 2015

8 Detailed Description

8.1 Overview

The LMH0318 is a 2.97Gbps/1.485Gbps/0.27Gbps multi-rate serial digital video data reclocker with integrated

cable driver intended for equalizing, reclocking, and driving data compatible to the SMPTE standards. It is a 2-

input, 2-output single-core chip, enabling 1:2 fan-out or 2:1 MUX operations. Each input has a 100

Ω continuous

time linear equalizer (CTLE) at the front-end, intended to compensate for loss over STP coax or FR-4 PCB trace.

The LMH0318 OUT0 is a 75

Ω cable driver compatible to the SMPTE requirements.

The referenceless Clock-and-Data Recovery (CDR) circuit selects between the two inputs based on user choice.

The reclocked output can be driven to one or two outputs. One of the outputs supports 100-

Ω differential cable

connection, while the other output can drive a 75

Ω SMPTE specified cable while meeting transmitter

requirements as specified in SMPTE standard. The LMH0318 locks to all required SDI data rates, including

270Mbps, 1.485 Gbps, 1.4835 Gbps, 2.97 Gbps, and 2.967 Gbps. The LMH0318 is assembled in a 4 mm × 4

mm 24-pin QFN package. The chip can be programmed using SPI or SMBus interface.

8.2 Functional Block Diagram

Submit Documentation Feedback

Product Folder Links: LMH0318

LMH0318RTWR Datasheet(PDF) 13 Page - Texas Instruments

LMH0318RTWR Datasheet(HTML) 13 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59

Datasheet Download

Link URL