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MSP430F423IPM.B Datasheet(PDF) 39 Page - Texas Instruments |
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MSP430F423IPM.B Datasheet(HTML) 39 Page - Texas Instruments |
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39 / 61 page ![]() P1OUT.x Module X OUT P1DIR.x Direction Control From Module P1SEL.x D EN Interrupt Edge Select P1IES.x P1SEL.x P1IE.x P1IFG.x P1IRQ.x EN Set Q 0 1 1 0 Pad Logic 0: Input 1: Output Bus keeper CAPD.x Module X IN P1IN.x P1.0/TA0 P1.1/TA0/MCLK 39 MSP430F427, MSP430F425, MSP430F423 www.ti.com SLAS421B – APRIL 2004 – REVISED NOVEMBER 2016 Submit Documentation Feedback Product Folder Links: MSP430F427 MSP430F425 MSP430F423 Detailed Description Copyright © 2004–2016, Texas Instruments Incorporated (1) Timer_A3 6.10 Input/Output Diagrams 6.10.1 Port P1 (P1.0 and P1.1) Input/Output With Schmitt Trigger Figure 6-8 shows the port diagram. Table 6-13 summarizes the selection of the port function. NOTE: 0 ≤ x ≤ 1. Port function is active if CAPD.x = 0. Figure 6-8. Port P1 (P1.0 and P1.1) Diagram Table 6-13. Port P1 (P1.0 and P1.1) Pin Function P1SEL.x P1DIR.x DIRECTION CONTROL FROM MODULE P1OUT.x MODULE X OUT P1IN.x MODULE X IN P1IE.x P1IFG.x P1IES.x CAPD.x P1SEL.0 P1DIR.0 P1DIR.0 P1OUT.0 Out0 Sig.(1) P1IN.0 CCI0A(1) P1IE.0 P1IFG.0 P1IES.0 DVSS P1SEL.1 P1DIR.1 P1DIR.1 P1OUT.1 MCLK P1IN.1 CCI0B(1) P1IE.1 P1IFG.1 P1IES.1 DVSS |
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