SBOU006 datasheet(21/33 Pages) TI2

21 / 33 page

OPA3691

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SBOS227E

output, but the circuit will still show very high forward and

reverse isolation. If configured as an inverting amplifier, the

input and output will be connected through the feedback

network resistance (RF + RG) giving relatively poor input to

output isolation.

One key parameter in disable operation is the output glitch

when switching in and out of the disable mode. Figure 14

shows these glitches for the circuit of Figure 1 with the input

signal set to 0V. The glitch waveform at the output pin is

plotted along with the DIS pin voltage.

FIGURE 14. Disable/Enable Glitch.

–10

–20

–30

Time (20ns/div)

6.0

4.0

2.0

0.0

As a worst-case example, compute the maximum TJ using an

OPA3691 SO-16 (see the circuit of Figure 1), operating at the

maximum specified ambient temperature of +85

°C with all

three outputs driving a grounded 20

Ω load to +2.5V:

PD = 10V • 17.1mA + 3 • [52/(4 • (20Ω || 804Ω))] = 1.13W

Maximum TJ = +85°C + (1.13 • 100°C/W) = 198°C

This absolute worst-case condition exceeds specified maxi-

mum junction temperature. Normally this extreme case will

not be encountered. Careful attention to internal power

dissipation is required and perhaps airflow considered under

extreme conditions.

BOARD LAYOUT GUIDELINES

Achieving optimum performance with a high-frequency am-

plifier like the OPA3691 requires careful attention to board

layout parasitics and external component types. Recommen-

dations that will optimize performance include:

a) Minimize parasitic capacitance to any AC ground for all

of the signal I/O pins. Parasitic capacitance on the output and

inverting input pins can cause instability: on the noninverting

input, it can react with the source impedance to cause

unintentional bandlimiting. To reduce unwanted capacitance,

a window around the signal I/O pins should be opened in all

of the ground and power planes around those pins. Other-

wise, ground and power planes should be unbroken else-

where on the board.

b) Minimize the distance (< 0.25") from the power-supply

pins to high-frequency 0.1

µF decoupling capacitors. At the

device pins, the ground and power plane layout should not

be in close proximity to the signal I/O pins. Avoid narrow

power and ground traces to minimize inductance between

the pins and the decoupling capacitors. The power-supply

connections (on pins 4 and 7) should always be decoupled

with these capacitors. An optional supply decoupling capaci-

tor across the two power supplies (for bipolar operation) will

improve 2nd-harmonic distortion performance. Larger (2.2

µF

to 6.8

µF) decoupling capacitors, effective at lower frequency,

should also be used on the main supply pins. These may be

placed somewhat farther from the device and may be shared

among several devices in the same area of the PCB.

c) Careful selection and placement of external compo-

nents will preserve the high-frequency performance of

the OPA3691. Resistors should be a very low reactance

type. Surface-mount resistors work best and allow a tighter

overall layout. Metal-film and carbon composition, axially

leaded resistors can also provide good high-frequency per-

formance. Again, keep their leads and PCB trace length as

short as possible. Never use wirewound type resistors in a

high-frequency application. Since the output pin and invert-

ing input pin are the most sensitive to parasitic capacitance,

always position the feedback and series output resistor, if

any, as close as possible to the output pin. Other network

components, such as noninverting input termination resis-

tors, should also be placed close to the package. Where

double-side component mounting is allowed, place the feed-

back resistor directly under the package on the other side of

the board between the output and inverting input pins. The

The transition edge rate (dv/dt) of the DIS control line will

influence this glitch. For the plot of Figure 14, the edge rate

was reduced until no further reduction in glitch amplitude was

observed. This approximately 1V/ns maximum slew rate may

be achieved by adding a simple RC filter into the V

DIS pin

from a higher speed logic line. If extremely fast transition

logic is used, a 2k

Ω series resistor between the logic gate

and the V

DIS input pin will provide adequate bandlimiting

using just the parasitic input capacitance on the V

DIS pin

while still ensuring adequate logic level swing.

THERMAL ANALYSIS

Due to the high output power capability of the OPA3691,

heatsinking or forced airflow may be required under extreme

operating conditions. Maximum desired junction temperature

will set the maximum allowed internal power dissipation as

described below. In no case should the maximum junction

temperature be allowed to exceed 175

°C. Operating junction

temperature (TJ) is given by TA + PD • θJA. The total internal

power dissipation (PD) is the sum of quiescent power (PDQ)

and additional power dissipation in the output stage (PDL) to

deliver load power. Quiescent power is simply the specified

no-load supply current times the total supply voltage across

the part. PDL will depend on the required output signal and

load but would, for a grounded resistive load, be at a

maximum when the output is fixed at a voltage equal to 1/2

of either supply voltage (for equal bipolar supplies). Under

this condition, PDL = VS2/(4 • RL) where RL includes feedback

network loading.

Note that it is the power in the output stage and not into the

load that determines internal power dissipation.

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