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PCM1802DB Datasheet(PDF) 17 Page - Texas Instruments |
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PCM1802DB Datasheet(HTML) 17 Page - Texas Instruments |
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17 / 35 page ![]() FORMAT 0: FMT[1:0] = 00 FORMAT 1: FMT[1:0] = 01 FORMAT 2: FMT[1:0] = 10 FORMAT 3: FMT[1:0] = 11 24-Bit, MSB-First, Left-Justified BCK LRCK Right-Channel Left-Channel DOUT 1 22 23 24 3 2 1 MSB LSB 22 23 24 3 2 1 MSB LSB FSYNC 24-Bit, MSB-First, I2S LRCK Right-Channel Left-Channel BCK DOUT 22 23 24 3 2 1 MSB LSB 22 23 24 3 2 1 MSB LSB FSYNC 24-Bit, MSB-First, Right-Justified LRCK Right-Channel Left-Channel BCK DOUT 24 22 23 24 3 2 1 MSB LSB 22 23 24 3 2 1 MSB LSB FSYNC 20-Bit, MSB-First, Right-Justified LRCK Right-Channel Left-Channel BCK DOUT 20 18 19 20 3 2 1 MSB LSB 18 19 20 3 2 1 MSB LSB FSYNC T0016-12 17 PCM1802 www.ti.com SLES023D – DECEMBER 2001 – REVISED DECEMBER 2016 Product Folder Links: PCM1802 Submit Documentation Feedback Copyright © 2001–2016, Texas Instruments Incorporated 7.4.2.2 Interface Timing Figure 24 and Figure 26 illustrate the interface timing in slave mode and master mode, respectively. Figure 23. Audio Data Format (Slave Mode: FSYNC, LRCK, and BCK Work as Inputs) |
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