PCM56P datasheet(6/18 Pages) TI2

6 / 18 page

PCM56

FIGURE 5. Total Harmonic Distortion (THD) vs Frequency.

INSTALLATION AND

OPERATING INSTRUCTIONS

POWER SUPPLY CONNECTIONS

For optimum performance and noise rejection, power supply

decoupling capacitors should be added as shown in the

Connection Diagram. These capacitors (1

µF tantalum or

electrolytic recommended) should be located close to the

converter.

MSB ERROR ADJUSTMENT PROCEDURE

(OPTIONAL)

The MSB error of the PCM56 can be adjusted to make the

differential linearity error (DLE) at BPZ essentially zero.

This is important when the signal output levels are very low,

because zero crossing noise (DLE at BPZ) becomes very

significant when compared to the small code changes

occurring in the LSB portion of the converter.

Differential linearity error at bipolar zero and THD are

guaranteed to meet data sheet specifications without any

external adjustment. However, a provision has been made

for an optional adjustment of the MSB linearity point which

makes it possible to eliminate DLE error at BPZ. Two

procedures are given to allow either static or dynamic

adjustment. The dynamic procedure is preferred because of

the difficulty associated with the static method (accurately

measuring 16-bit LSB steps).

To statically adjust DLE at BPZ, refer to the circuit shown

in Figure 6, or the PCM56 connection diagram.

After allowing ample warm-up time (5-10 minutes) to assure

stable operation of the PCM56, select input code FFFF

hexadecimal (all bits on except the MSB). Measure the

audio output voltage using a 6-1/2 digit voltmeter and record

it. Change the digital input code to 0000 hexadecimal (all

bits off except the MSB). Adjust the 100k

Ω potentiometer to

make the audio output read 92

µV more than the voltage

reading of the previous code (a 1LSB step = 92

µV).

A much simpler method is to dynamically adjust the DLE at

BPZ. Again, refer to Figure 6 for circuitry and component

values. Assuming the device has been installed in a digital

audio application circuit, send the appropriate digital input

to produce a –80dB level sinusoidal output. While measuring

the THD of the audio circuit output, adjust the 100k

Ω

potentiometer until a minimum level of distortion is observed.

INPUT TIMING CONSIDERATIONS

Figure 7 and 8 refer to the input timing required to interface

the inputs of PCM56 to a serial input data stream. Serial data

is accepted in Binary Two’s Complement (BTC) with the

MSB being loaded first. Data is clocked in on positive going

clock (CLK) edges and is latched into the DAC input

The latch enable input must be high for at least one clock

cycle before going low, and then must be held low for at

least one clock cycle. The last 16 data bits clocked into the

serial input register are the ones that are transferred to the

DAC input register when latch enable goes low. In other

words, when more than 16 clock cycles occur between a

latch enable, only the data present during the last 16 clocks

will be transferred to the DAC input register.

One requirement for clocking in all 16 bits is the necessity

for a “17th” clock pulse. This automatically occurs when the

clock is continuous (last bit shifts in on the first bit of the

next data word). If the clock is stopped between input of 16-

bit data words, the latch enable (LE) must remain low until

after the first clock of the next 16-bit data word stream. This

ensures that the latch is properly set up.

Figure 7 refers to the general input format required for the

PCM56. Figure 8 shows the specific relationships between

the various signals and their timing constraints.

INSTALLATION

CONSIDERATIONS

If the optional external MSB error circuitry is used, a

potentiometer with adequate resolution and a TCR of 100ppm/

°C or less is required. Also, extra care must be taken to

insure that no leakage path (either AC or DC) exists to pin

14. If the circuit is not used, pins 14 and 15 should be left

open.

The PCM converter and the wiring to its connectors should

be located to provide the optimum isolation from sources of

RFI and EMI. The important consideration in the elimination

FIGURE 6. MSB Adjustment Circuit.

Frequency (Hz)

100

0.1

0.01

0.001

10k

20k

(Full Scale)

(–20dB)

470k

Ω

100k

Ω

200k

Ω

Trim 15

MSB Adjust 14

1 –V

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