Crystal

PLL1707

Crystal

OSC

Circuit

27-MHz

Internal

Master

Clock

XT1

XT2

C2

C1

MCKO1

MCKO2

C1, C2 = 10 pF to 33 pF

Crystal Resonator Connection

PLL1707

XT1

XT2

MCKO1

MCKO2

External Clock Input Connection

External

Clock

Crystal

OSC

Circuit

27-MHz

Internal

Master

Clock

t(XT1H)

XT1

t(XT1L)

0.7 VCC

0.3 VCC

PLL1707-Q1

SLES259A

– JUNE 2010 – REVISED MARCH 2011

www.ti.com

Figure 8. Master Clock Generator Connection Diagram

Figure 9. External Master Clock Timing Requirements

Table 1. External Master Clock Timing Requirements

DESCRIPTION

SYMBOL

MIN

MAX

UNIT

Master clock pulse duration HIGH

t(XT1H)

10

ns

Master clock pulse duration LOW

t(XT1L)

10

ns

The PLL1707 provides a very low-jitter high-accuracy clock. SCKO0 outputs a fixed 33.8688-MHz clock, SCKO1

outputs 512 fS or 768 fS (fS = 48 kHz), which is selected by hardware or software control (see Table 2). The

output frequency of the remaining clocks is determined by the sampling frequency (fS) under hardware or

software control. SCKO2 and SCKO3 output 256-fS and 384-fS system clocks, respectively. Table 3 shows each

sampling frequency which can be programmed. The system clock output frequencies for programmed sampling

frequencies are shown in Table 4.

Table 2. Generated System Clock SCKO1 Frequency

fS

SCKO1 FREQUENCY

512 fS

24.576 MHz

768 fS

36.864 MHz

Table 3. Sampling Frequencies

SAMPLING RATE

SAMPLING FREQUENCY (kHz)

Standard sampling frequencies

32

44.1

48

Double sampling frequencies

64

88.2

96

8

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