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SN74LVC240APWR Datasheet(PDF) 9 Page - Texas Instruments |
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SN74LVC240APWR Datasheet(HTML) 9 Page - Texas Instruments |
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9 / 30 page ![]() 1 2 4 6 8 19 11 13 15 17 3 5 7 9 12 14 16 18 1A1 1A2 1A3 1A4 1Y1 2A1 2A2 2A3 2A4 2Y1 1Y2 1Y3 1Y4 2Y2 2Y3 2Y4 1OE 2OE SN74LVC240A www.ti.com SCAS293L – JANUARY 1993 – REVISED JULY 2014 9 Detailed Description 9.1 Overview This device is organized as two 4-bit buffers/drivers with separate output-enable (OE) inputs. When OE is low, the device passes data from the A inputs to the Y outputs. When OE is high, the outputs are in the high- impedance state. Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in a mixed 3.3-V/5-V system environment. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. 9.2 Functional Block Diagram Copyright © 1993–2014, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Links: SN74LVC240A |
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