TMP411CD datasheet(16/48 Pages) TI2

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t(BUF)

SDA

SCL

t(HDSTA)

t(HDDAT)

t(HIGH)

t(SUSTA)

t(SUDAT)

t(LOW)

t(HDSTA)

t(SUSTO)

TMP411

SBOS383D – DECEMBER 2006 – REVISED DECEMBER 2016

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Programming (continued)

9.5.2 Bus Overview

The TMP411 is SMBus interface-compatible. In SMBus protocol, the device that initiates the transfer is a master,

and the master controls devices known as slaves. The bus must be controlled by a master device that generates

the serial clock (SCL), controls the bus access, and generates the START and STOP conditions.

To address a specific device, a START condition is initiated. START is indicated by pulling the data line (SDA)

from a high to low logic level while the SCL line is high. All slaves on the bus shift are in the slave address byte,

with the last bit indicating if a read or write operation is needed. During the ninth clock pulse, the slave that is

addressed responds to the master by generating an acknowledge bit and pulling the SDA line low.

Data transfer is then initiated and sent over eight clock pulses followed by an acknowledge bit. During data

transfer, the SDA line must remain stable while the SCL is high. A change in the SDA while the SCL is high is

interpreted as a control signal.

Once all data transfers, the master generates a STOP condition. STOP is indicated by pulling the SDA line from

low to high, while the SCL line is high.

9.5.3 Timing Diagrams

The TMP411 is two-wire and SMBus-compatible. Figure 12 to Figure 16 describe the various operations on the

TMP411. Parameters for Figure 12 are defined in the Timing Requirements section. Bus definitions are given

below:

Bus Idle: Both SDA and SCL lines remain high.

Start Data Transfer: A change in the state of the SDA line, from high to low (while the SCL line is high) defines

a START condition. A START condition initiates each data transfer.

Stop Data Transfer: A change in the state of the SDA line from low to high (while the SCL line is high) defines a

STOP condition. A STOP or repeated START condition terminates each data transfer.

Data Transfer: The number of data bytes transferred between a START and a STOP condition is not limited and

is determined by the master device. The receiver acknowledges the data transfer.

Acknowledge: Each receiving device (when addressed) is required to generate an acknowledge bit. A device

that acknowledges must pull the SDA line down during the acknowledge clock pulse so the SDA line is stable

and low during the high period of the acknowledge clock pulse. Setup and hold times must be taken into account.

On a master receive, the master signals data transfer termination by generating a not-acknowledge bit

transmitted by the slave.

Figure 12. Two-Wire Timing Diagram

TMP411CD Datasheet(PDF) 16 Page - Texas Instruments

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