485

TOP VIEW

NOTE: PIN LABELS Y AND Z ON TIMING, TEST, AND WAVEFORM DIAGRAMS REFER TO PINS A AND B WHEN DE IS HIGH.

TYPICAL OPERATING CIRCUIT SHOWN WITH DIP/SO PACKAGE.

1

2

3

4

8

5

VCC

GND

DI

DE

RE

RO

R

D

Rt

Rt

7

6

D

R

DE

RE

DI

RO

A

B

1

2

3

4

8

7

6

5

VCC

B

A

GND

DI

DE

RE

RO

DIP/SO

R

D

1

2

3

4

8

7

6

5

VCC

A

GND

DE

RE

B

RO

µMAX

B

A

DI

485 Pin Configuration and Typical Operating Circuit

TTL IN

tR, tF < 6ns

D

R

100pF

B

100pF

A

RECEIVER

OUT

R = 54Ω

Z

Y

500mV/div

20ns/div

A

B

RO

2V/div

VCC = 5V

TA = +25°C

500mV/div

20ns/div

A

B

RO

2V/div

VCC = 5V

TA = +25°C

Receiver Propagation Delay Test Circuit

485 Receiver tPHL

485 Receiver tPLH

XL485-SS

MSOP8

XL485CS

XD485

RS-485/RS422

SOP8

DIP-8

5